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detectors [2013/12/13 19:10]
pereira [Cathode Readout Drift Chambers (CRDC)] |
detectors [2013/12/13 19:14]
pereira [Cathode Readout Drift Chambers (CRDC)] |
| Each detector consists of two windows mounted on frames, two printed circuit boards (PCB) and an anode frame. Each PCB is made of un-masked G-10, and includes a field shaping foil to ensure a uniform field in the active region of the detector. Two G-10 spacers are laminated to the board on each side. The shaping foils are made of 1.9-mm pitch evaporated aluminum strips perpendicularly oriented to the electric field. The anode frame includes a glued cathode grounding plane, an anode wire running across the field, and a Frisch grid. Cathode pads are located in front of and behind the anode wire. The pads have a pitch of 2.54 mm. The anode frame is sandwiched between the two printed circuit boards with two spacers in between, as shown in the figure below. | Each detector consists of two windows mounted on frames, two printed circuit boards (PCB) and an anode frame. Each PCB is made of un-masked G-10, and includes a field shaping foil to ensure a uniform field in the active region of the detector. Two G-10 spacers are laminated to the board on each side. The shaping foils are made of 1.9-mm pitch evaporated aluminum strips perpendicularly oriented to the electric field. The anode frame includes a glued cathode grounding plane, an anode wire running across the field, and a Frisch grid. Cathode pads are located in front of and behind the anode wire. The pads have a pitch of 2.54 mm. The anode frame is sandwiched between the two printed circuit boards with two spacers in between, as shown in the figure below. |
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| {{:wiki:crdc-section.jpg?600|Cross section of a CRDCs.}} | {{:wiki:crdc-section.jpg?600 |Cross section of a CRDCs.}} |
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| {{:wiki:crdc-section-drift.jpg?500|Principle of operation of a CRDC.}} | {{:wiki:crdc-section-drift.jpg?400 |Principle of operation of a CRDC.}} |
| Both CRDCs are equipped with digital electronics, which consist of seven front-end electronic boards (FEE) designed and developed by the [[http://www.star.bnl.gov/|STAR collaboration]] ([[http://www.bnl.gov/rhic/|RHIC]]), followed by interface boards connected to a programmable FPGA VME module ([[http://wwwp.cord.edu/dept/physics/mona/manuals/XLM72UM.pdf|XLM72]]) like the one used with the [[Detectors#Tracking Parallel Plate Avalanche Counters (TPPAC)|TPPACs]] in the intermediate image station. Each FEE includes 32 channels of preamplifier shaper, followed by a switch capacitor array (SCA) and an ADC. The processing of signals is driven by the FPGA module. Each SCA samples the signals after a valid trigger is received and sends the information into the ADC. The digitized data are then stored into the internal memory of the FPGA and read out in block mode. The sampling frequency and number of samples read out are adjustable; typical values are 20 MHz and 8 to 12 samples. The time needed for each sampling is around 16 µs. Thus, the dead time of the electronics is directly proportional to the number of samples read out. The main advantage of the on-detector digitalization technique used with the CRDCs is the reduction of noise by avoiding the transmission of analog signals (448 from the two CRDCs) outside the vacuum chamber, and the possibility to record multi-hit events like in traditional TPC detectors. | Both CRDCs are equipped with digital electronics, which consist of seven front-end electronic boards (FEE) designed and developed by the [[http://www.star.bnl.gov/|STAR collaboration]] ([[http://www.bnl.gov/rhic/|RHIC]]), followed by interface boards connected to a programmable FPGA VME module ([[http://wwwp.cord.edu/dept/physics/mona/manuals/XLM72UM.pdf|XLM72]]) like the one used with the [[Detectors#Tracking Parallel Plate Avalanche Counters (TPPAC)|TPPACs]] in the intermediate image station. Each FEE includes 32 channels of preamplifier shaper, followed by a switch capacitor array (SCA) and an ADC. The processing of signals is driven by the FPGA module. Each SCA samples the signals after a valid trigger is received and sends the information into the ADC. The digitized data are then stored into the internal memory of the FPGA and read out in block mode. The sampling frequency and number of samples read out are adjustable; typical values are 20 MHz and 8 to 12 samples. The time needed for each sampling is around 16 µs. Thus, the dead time of the electronics is directly proportional to the number of samples read out. The main advantage of the on-detector digitalization technique used with the CRDCs is the reduction of noise by avoiding the transmission of analog signals (448 from the two CRDCs) outside the vacuum chamber, and the possibility to record multi-hit events like in traditional TPC detectors. |
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