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--- detectors [2013/12/20 15:02]
pereira [Plastic scintillators]
+++ detectors [2013/12/26 12:23]
pereira [Detectors]
@@ Line 1: / Line 1: @@
 ====== Detectors ======
-The standard detection system of the S800 consists of a [[Detectors#Plastic scintillators|plastic scintillator]] at the object station; two tracking detector at the intermediate plane station ([[Detectors#Tracking Parallel Plate Avalanche Counters (TPPAC)|TPPAC]]) and a series of detectors at the focal plane station (see figure below), which include two cathode readout drift chambers ([[Detectors#Cathode Readout Drift Chambers (CRDC)|CRDC]]) located about 1 m apart; a [[Detectors#Ionization Chamber|multi-segmented ionization chamber]], a thin [[Detectors#Plastic scintillators|plastic scintillators]] and a [[Detectors#Hodoscope|Hodoscope]].
+The standard detection system of the S800 consists of a [[Detectors#Plastic scintillators|plastic scintillator]] at the [[Stations#Object Station|object station]]; two tracking detector at the [[Stations#Intermediate Plane Station|intermediate plane station]] ([[Detectors#Tracking Parallel Plate Avalanche Counters (TPPAC)|TPPAC]]) and a series of detectors at the focal plane station (see figure below), which include two cathode readout drift chambers ([[Detectors#Cathode Readout Drift Chambers (CRDC)|CRDC]]) located about 1 m apart; a [[Detectors#Ionization Chamber|multi-segmented ionization chamber]], a thin [[Detectors#Plastic scintillators|plastic scintillators]] and a [[Detectors#Hodoscope|Hodoscope]].
 {{:wiki:s800-fp-detectors.jpg?650|S800 detector station at the Focal Plane.}}
@@ Line 44: / Line 44: @@
 {{:wiki:crdc-section-drift.jpg?400 |Principle of operation of a CRDC.}}
-Both  CRDCs are equipped with digital electronics, which consist of seven front-end electronic boards (FEE) designed and developed by the [[http://www.star.bnl.gov/|STAR collaboration]] ([[http://www.bnl.gov/rhic/|RHIC]]), followed by interface boards connected to a programmable FPGA VME module ([[http://wwwp.cord.edu/dept/physics/mona/manuals/XLM72UM.pdf|XLM72]]) like the one used with the [[Detectors#Tracking Parallel Plate Avalanche Counters (TPPAC)|TPPACs]] in the intermediate image station. Each FEE includes 32 channels of preamplifier shaper, followed by a switch capacitor array (SCA) and an ADC. The processing of signals is driven by the FPGA module. Each SCA samples the signals after a valid trigger is received and sends the information into the ADC. The digitized  data are then stored into the internal memory of the FPGA and read out in block mode. The sampling frequency and number of samples read out are adjustable; typical values are 20 MHz and 8 to 12 samples. The time needed for each sampling is around 16 µs. Thus, the dead time of the electronics is directly proportional to the number of samples read out. The main advantage of the on-detector digitalization technique used with the CRDCs is the reduction of noise by avoiding the transmission of analog signals (448 from the two CRDCs) outside the vacuum chamber, and the possibility to record multi-hit events like in traditional TPC detectors.
+Both  CRDCs are equipped with digital electronics, which consist of seven front-end electronic boards (FEE) designed and developed by the [[http://www.star.bnl.gov/|STAR collaboration]] ([[http://www.bnl.gov/rhic/|RHIC]]), followed by interface boards connected to a programmable FPGA VME module ([[http://wwwp.cord.edu/dept/physics/mona/manuals/XLM72UM.pdf|XLM72]]) like the one used with the [[Detectors#Tracking Parallel Plate Avalanche Counters (TPPAC)|TPPACs]] in the intermediate image station. Each FEE includes 32 channels of preamplifier shaper, followed by a switch capacitor array (SCA) and an ADC. The processing of signals is driven by the FPGA module. Each SCA samples the signals after a valid trigger is received and sends the information into the ADC. The digitized  data are then stored into the internal memory of the FPGA and read out in block mode. The sampling frequency and number of samples read out are adjustable; typical values are 20 MHz and 8 to 12 samples. The time needed for each sampling is around 16 µs. Thus, the dead time of the electronics is directly proportional to the number of samples read out. The main advantage of the on-detector digitalization technique used with the CRDCs is the reduction of noise by avoiding the transmission of analog signals (448 from the two CRDCs) outside the vacuum chamber, and the possibility to record multi-hit events like in traditional TPC detectors. The schematic diagram of the firmware for the reading of the XLM72V FPGA can be found {{:wiki:Crdc5v.pdf|here}}
+here
-===== Ionization Chamber =====
+===== Ionization chamber =====
 An ionization chamber downstream of both [[Detectors#Cathode Readout Drift Chambers (CRDC)|CRDCs]] is used to identify the Z number of the transmitted nuclei from their energy loss. The detector has an active volume of __xxx cm x xxx cm x xxx cm__ and is filled with P10 gas (90% argon, 10% methane) at a typical pressure of 300 torr, although this value can be increased up to 600 torr for light nuclei. The detector consists of 16 stacked-parallel plate ion chambers with narrow anode-cathode gaps, placed along the detector’s central axis, perpendicular to the beam direction (see left figure below ). The plates are constructed from 70 mg/cm<sup>2</sup> polypropylene with 0.05 µm of aluminum evaporated on each side. The entrance and exit windows of the chamber are made of 14 mg/cm<sup>2</sup> Mylar with an overlay of Kevlar filaments and epoxy.
@@ Line 59: / Line 60: @@
 {{:wiki:ion-chamber-picture.jpg?500 |Picture of the S800 ionization chamber with its alternating cathode and anode plates.}}
 {{ :wiki:ion-chamber-drawing.jpg?500|Schematic representation of the principle of operation of the ionization chamber.}}

S800 Documentation

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