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detectors [2019/04/09 14:23] pereira [Detectors] |
detectors [2019/04/09 14:24] pereira [Hodoscope] |
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{{:wiki:crdc-section-drift.jpg?400 |Principle of operation of a CRDC.}} | {{:wiki:crdc-section-drift.jpg?400 |Principle of operation of a CRDC (figure taken from K. Meierbachtol PhD thesis, MSU, 2012).}} |
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Both CRDCs are equipped with digital electronics, which consist of seven front-end electronic boards (FEE) designed and developed by the [[http://www.star.bnl.gov/|STAR collaboration]] ([[http://www.bnl.gov/rhic/|RHIC]]), followed by interface boards connected to a programmable FPGA VME module ({{:wiki:Manual_JTEC_XLM72VUM.pdf|XLM72}}) like the one used with the [[Detectors#Tracking Parallel Plate Avalanche Counters (TPPAC)|TPPACs]] in the intermediate image station. Each FEE includes 32 channels of preamplifier shaper, followed by a switch capacitor array (SCA) and an ADC. The processing of signals is driven by the FPGA module. Each SCA samples the signals after a valid trigger is received and sends the information into the ADC. The digitized data are then stored into the internal memory of the FPGA and read out in block mode. The sampling frequency and number of samples read out are adjustable; typical values are 20 MHz and 8 to 12 samples. The time needed for each sampling is around 16 µs. Thus, the dead time of the electronics is directly proportional to the number of samples read out. The main advantage of the on-detector digitalization technique used with the CRDCs is the reduction of noise by avoiding the transmission of analog signals (448 from the two CRDCs) outside the vacuum chamber, and the possibility to record multi-hit events like in traditional TPC detectors. The schematic diagram of the firmware for the reading of the XLM72V FPGA can be found {{:wiki:Crdc5v.pdf|here}}. | Both CRDCs are equipped with digital electronics, which consist of seven front-end electronic boards (FEE) designed and developed by the [[http://www.star.bnl.gov/|STAR collaboration]] ([[http://www.bnl.gov/rhic/|RHIC]]), followed by interface boards connected to a programmable FPGA VME module ({{:wiki:Manual_JTEC_XLM72VUM.pdf|XLM72}}) like the one used with the [[Detectors#Tracking Parallel Plate Avalanche Counters (TPPAC)|TPPACs]] in the intermediate image station. Each FEE includes 32 channels of preamplifier shaper, followed by a switch capacitor array (SCA) and an ADC. The processing of signals is driven by the FPGA module. Each SCA samples the signals after a valid trigger is received and sends the information into the ADC. The digitized data are then stored into the internal memory of the FPGA and read out in block mode. The sampling frequency and number of samples read out are adjustable; typical values are 20 MHz and 8 to 12 samples. The time needed for each sampling is around 16 µs. Thus, the dead time of the electronics is directly proportional to the number of samples read out. The main advantage of the on-detector digitalization technique used with the CRDCs is the reduction of noise by avoiding the transmission of analog signals (448 from the two CRDCs) outside the vacuum chamber, and the possibility to record multi-hit events like in traditional TPC detectors. The schematic diagram of the firmware for the reading of the XLM72V FPGA can be found {{:wiki:Crdc5v.pdf|here}}. |
The hodoscope is composed 32 sodium-doped cession iodide CsI(Na) scintillating crystals manufactured by [[http://www.scintitech.com/|ScintiTech]]. Each crystal is 5.1 cm-thick, has an active area of 7.6 cm x 7.6 cm, and is attached to a photomultiplier ([[https://www.hamamatsu.com/jp/en/R1307.html|Hamamatsu R1307]]). The photo-cathodes are made of a bi-alkali material with a transmission peak at 420 nm. The 32 crystals are arranged in eight rows of 4 crystals each so as to cover approximately the same solid angle than the [[Detectors#Cathode Readout Drift Chambers (CRDC)|CRDCs]]. The frontal and lateral sides of each crystal are covered with two 150-µm thick layers of a white Teflon reflective material to provide light shielding between the crystals. The photocathodes are connected to a [[https://groups.nscl.msu.edu/nscl_library/manuals/caen/MOD.N568B.pdf|CAEN N568B]] 16-channel shaper/amplifier, followed by a [[https://groups.nscl.msu.edu/nscl_library/manuals/phillips/7164H.pdf|Phillips 7164H]] 12-bit ADC. The signals from the crystals are gain-matched to a middle position in the ADC spectra by varying the biases of each photocathode. | The hodoscope is composed 32 sodium-doped cession iodide CsI(Na) scintillating crystals manufactured by [[http://www.scintitech.com/|ScintiTech]]. Each crystal is 5.1 cm-thick, has an active area of 7.6 cm x 7.6 cm, and is attached to a photomultiplier ([[https://www.hamamatsu.com/jp/en/R1307.html|Hamamatsu R1307]]). The photo-cathodes are made of a bi-alkali material with a transmission peak at 420 nm. The 32 crystals are arranged in eight rows of 4 crystals each so as to cover approximately the same solid angle than the [[Detectors#Cathode Readout Drift Chambers (CRDC)|CRDCs]]. The frontal and lateral sides of each crystal are covered with two 150-µm thick layers of a white Teflon reflective material to provide light shielding between the crystals. The photocathodes are connected to a [[https://groups.nscl.msu.edu/nscl_library/manuals/caen/MOD.N568B.pdf|CAEN N568B]] 16-channel shaper/amplifier, followed by a [[https://groups.nscl.msu.edu/nscl_library/manuals/phillips/7164H.pdf|Phillips 7164H]] 12-bit ADC. The signals from the crystals are gain-matched to a middle position in the ADC spectra by varying the biases of each photocathode. |
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{{:wiki:hodoscope-drawing.jpg?500 |Schematic layout of the S800 Hodoscope.}} | {{:wiki:hodoscope-drawing.jpg?500 |Schematic layout of the S800 Hodoscope (figure taken from K. Meierbachtol PhD thesis, MSU, 2012).}} |
{{ :wiki:hodoscope-picture.jpg?450|Backface of the S800 Hodoscope.}} | {{ :wiki:hodoscope-picture.jpg?450|Backface of the S800 Hodoscope (figure taken from K. Meierbachtol PhD thesis, MSU, 2012).}} |
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