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electronics [2013/10/23 20:48] pereira |
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====== Electronics ====== | ====== Electronics ====== | ||
+ | * [[Electronics# | ||
+ | * [[Electronics# | ||
+ | * [[Electronics# | ||
+ | * [[Trigger|Trigger]] | ||
- | ===== General description ===== | ||
- | The trigger of the S800 offers the possibility to combine the S800 trigger with triggers from other detectors or arrays in order to form coincidences. This is often a mandatory requirement when the trigger rate of the S800 alone (S800 singles) is too high for the data acquisition and the resulting dead time is prohibitive. | ||
- | Because | + | ===== Crate Configuration ===== |
+ | A preliminary scheme of the crate configuration (in progress) can be found {{: | ||
+ | ===== Inventory Modules ===== | ||
+ | In progress. | ||
- | ===== Schematics ===== | ||
- | The trigger logic of the S800 is implemented in a FPGA driven module. Apart from reducing the cabling and number of modules, this module allows the user to remotely control and inspect trigger signals, even while beam is present in the vault. In addition, the trigger configuration can be saved and restored at any time. | ||
- | The FPGA module uses the LeCroy 2367 Universal Logic Module to implement the S800 trigger logic by means of its XC4000E Xilinx FPGA. The main purpose of the trigger is to implement a coincidence between the S800 focal plane and a secondary detector principally located at the target location. | + | ===== Electronic Diagrams ===== |
- | + | | |
- | + | * {{: | |
- | The S800 trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | + | * {{: |
- | + | * {{:wiki:tppacelectronics.pdf|Tracking PPAC Schematic Electronics Diagram}} | |
- | {{:wiki:800px-TriggerGUI.png?700|Layout of the S800}} | + | * {{:wiki:trigger_scheme.pdf|Trigger Schematic Electronics Diagram}} |
- | + | | |
- | The two main trigger sources are labeled " | + | |
- | + | ||
- | The S800 trigger source comes from the fast timing scintillator [[Detectors# | + | |
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- | + | ||
- | ===== Trigger Box ===== | + | |
- | In addition to the singles and coincidence triggers, two separate inputs called " | + | |
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- | + | ||
- | ===== Time stamping ===== | + | |
- | As the S800 USB-based data acquisition uses independent crate controllers, | + | |
- | + | ||
- | The trigger module FPGA configuration contains a 64 bit counter which is latched by the "Live trigger" | + | |
- | + | ||
- | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. | + | |
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- | + | ||
- | ===== Busy circuit ===== | + | |
- | As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The global busy signal is formed by a logical OR of all busy signals. To eliminate delays caused by the cables routing the individual signals, the S800 trigger uses local latches that are set by the trigger signal and reset by the individual end-of-event signals. The length of the global busy is then determined by the slowest readout sequence. | + | |
- | + | ||
- | The busy circuit following the generation of raw triggers is mainly composed of a latch that is set by the "Raw trigger" | + | |
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- | + | ||
- | ===== Gate generation ===== | + | |
- | All digitizer gates and start signals are derived from the live trigger signal, with the exception of the QDC gate which is directly generated from the S800 source signal. The reason is to avoid long analog delays on the scintillator signals. A fast clear circuit is provided to clear the QDC if no valid trigger was generated. | + | |
- | Inspect channels | + | |
- | A set of four inspect channels are patched out to the Data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit. | + | |
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- | ===== VME time stamp XLM72 module ===== | + | |
- | The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. This section describes the firmware used to configure this module into a 64 bit latched time stamp module. The inputs are the following: | + | |
- | E1: time stamp clock input | + | |
- | E2: latch input | + | |
- | E3: clear input | + | |
- | The clear can be done via software as well, and is usually done that way. | + | |
- | The schematics of the firmware can be is available. | + | |
- | + | ||
- | Configuration for S800 in tandem with other detectors | + | |
- | In its standard configuration, | + | |
- | To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following: | + | |
- | • Raw trigger from external detector to Secondary source | + | |
- | • Live trigger from S800 trigger to external data acquisition (trigger input) | + | |
- | • Time stamp clock from S800 trigger to external data acquisition (time stamp input) | + | |
- | • End-of-event from external data acquisition to S800 trigger | + | |
- | • Busy from external data acquisition to S800 trigger | + | |
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- | Time stamping scheme================= | + | |
- | The S800 trigger provides a vetoed 10 MHz clock signal used for time stamping (an external clock can also be used). The clock is inhibited by a " | + | |
- | Busy scheme | + | |
- | As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The global busy signal is formed by a logical OR of all busy signals. To eliminate delays caused by the cables routing the individual signals, the S800 trigger uses local latches that are set by the trigger signal and reset by the individual end-of-event signals. The length of the global busy is then determined by the slowest readout sequence. | + | |