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--- electronics [2013/10/23 20:51]
pereira
+++ electronics [2013/12/12 12:24]
pereira [Electronics]
@@ Line 1: / Line 1: @@
 ====== Electronics ======
+  * [[Electronics#Crate Configuration|Crate Configuration]]
+  * [[Electronics#Inventory Modules|Inventory Modules]]
+  * [[Electronics#Electronic Diagrams|Electronic Diagrams]]
+  * [[Electronics#Documentation|Documentation]]
+  * [[Trigger|Trigger]]
+     * [[Trigger#Trigger schemaatics|Trigger schematic]]
+       * Trigger box
+       * Gate generation
+       * Inspect channels
+       * Busy Circuit
+       * Time Stamping Scheme
+     * Trigger module
+       * CAMAC commands
+       * Inputs and outputs
+       * FPGA firmware
+     * Time stamping
+     * Configuration for S800 in tandem with other detectors
+     * Begin sequence
+     * Scalers and dead time
-===== General description =====
+===== Crate Configuration =====
-The trigger of the S800 offers the possibility to combine the S800 trigger with triggers from other detectors or arrays in order to form coincidences. This is often a mandatory requirement when the trigger rate of the S800 alone (S800 singles) is too high for the data acquisition and the resulting dead time is prohibitive.
+A preliminary scheme of the crate configuration (in progress) can be found {{:wiki:s800electronicstcrateconfiguration2.pdf|here}}.
-Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward.
+===== Inventory Modules =====
+In progress.
-===== Schematics =====
+===== Electronic Diagrams =====
-The trigger logic of the S800 is implemented in a FPGA driven module. Apart from reducing the cabling and number of modules, this module allows the user to remotely control and inspect trigger signals, even while beam is present in the vault. In addition, the trigger configuration can be saved and restored at any time.
+  * {{:wiki:s800electronicstschematics_to20131125.pdf|Main Electronic Diagram}}
+  * {{:wiki:crdcdiagram.pdf|CRDC Schematic Electronic Diagram}}
+  * {{:wiki:ionchamber.pdf|Ion Chamber Schematic Electronics Diagram}}
+  * {{:wiki:tppacelectronics.pdf|Tracking PPAC Schematic Electronics Diagram}}
+  * {{:wiki:trigger_scheme.pdf|Trigger Schematic Electronics Diagram}}
+  * {{:wiki:fasttimimg.pdf|Fast Timing Schematic Electronics Diagram}}
-The FPGA module uses the LeCroy 2367 Universal Logic Module to implement the S800 trigger logic by means of its XC4000E Xilinx FPGA. The main purpose of the trigger is to implement a coincidence between the S800 focal plane and a secondary detector principally located at the target location.
-The S800 trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below.
+===== Documentation =====
-{{:wiki:800px-TriggerGUI.png?700|Layout of the S800}}
+  * Manuals for electronic modules
+      * {{:wiki:Manual_JTEC_XLM72VUM.pdf|Manual for the XLM72V (Virtex FPGA) module}}
-The two main trigger sources are labeled "S800" and "Secondary" in the GUI. Each source is routed to a gate and delay generator before forming a coincidence in the following AND gate. In addition, each source goes to delay generator followed by a downscaler. The purpose of the latter branch is to provide singles triggers for both sources. The coincidence is widened by a gate generator before being ANDed with the delayed S800 source signal. This last part of the coincidence circuit is used to ensure that the timing of the coincidence is always governed by the S800 signal. Note that each Gate and Delay generator can be bypassed.
+      * {{:wiki:manual_vm-usb_9_01_1.pdf|Manual for the VM-USB Wiener module}}
+      * {{:wiki:manual_cc-usb_502_0.pdf|Manual for the CC-USB Wiener module}}
-The S800 trigger source comes from the fast timing scintillator [[Detectors#Plastic scintillators|E1]] located in the focal plane, and always provides the reference time for the [[Detectors#Cathode Readout Drift Chambers (CRDC)|CRDCs]] as well as time-of-flight measurements. Note that because the FPGA uses a 40 MHz internal clock the time reference of the signals in the trigger circuit are set the phase of that clock, and therefore jitter by 25 ns with respect to the source signals. This jitter is measured with a TDC and can be subtracted to the time measurements to recover the timing relative to the source signals.
+      * {{:wiki:Manual_LeCroy_ULM_2367.pdf|Manual for the ULM LeCroy 2367 module}}
+      * {{:wiki:Manual_LeCroy_CFD_612a.pdf|Manual for the CFD LeCroy 612a module}}
+      * {{:wiki:Manual_LeCroy_CFD_4413.pdf|Manual for the CFD LeCroy 4413 module}}
-===== Trigger Box =====
+      * {{:wiki:Manual_LeCroy_CoincReg_4448.pdf|Manual for the Coincidence Register LeCroy 4448 module}}
-In addition to the singles and coincidence triggers, two separate inputs called "External 1" and "External 2" can be used as trigger sources. All sources can be independently selected by selecting the appropriate check box in the trigger box (see figure above), which is a logical OR of all five inputs. This means in case more than one trigger source is selected, it is possible that more than one pulse is generated at the output, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" output of the trigger box may generate two pulses for a single event. A scaler connected to the "Raw trigger" output will therefore not reflect the true number of events. For this reason scalers are also connected to individual inputs of the trigger box. A trigger register word (bit pattern) is written at each occurrence of a live trigger signal. This word is the first being read out from the trigger module, prior to the time stamp.
+      * {{:wiki:Manual_LeCroy_Scaler_4434.pdf|Manual for the Scaler LeCroy 4434 module}}
+      * {{:wiki:Manual_LeCroy_FERA_4300b.pdf|Manual for the FERA LeCroy 4300b module}}
+      * {{:wiki:Manual_Tennelec_Amplifier_TC241S.pdf|Manual for the Amplifier Tennelec TC241S module}}
-===== Time stamping =====
+      * {{:wiki:Manual_Phillips_LogicUnit_755.pdf|Manual for the Logic Unit Phillips 755 module}}
-As the S800 USB-based data acquisition uses independent crate controllers, time stamping between the crates is required in order to synchronize the events properly. The same synchronization scheme can be used when coupling external data acquisition systems to the S800.
+      * {{:wiki:Manual_Phillips_CFD_7186.pdf|Manual for the CFD Phillips 7186module}}
+      * {{:wiki:Manual_Phillips_ADC_7164H.pdf|Manual for the ADC Phillips 7164H module}}
-The trigger module FPGA configuration contains a 64 bit counter which is latched by the "Live trigger" signal, and used to time stamp the events. The clock used by default is an internal 10 MHz clock derived from the 40 MHz FPGA clock, although any external clock can also be used, after selecting the appropriate check box in the GUI. The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset, typically during the begin sequences of the controllers or data acquisitions. The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme ensures that all time stamp counters are synchronized.
+      * {{:wiki:Manual_Phillips_ADC_7164.pdf|Manual for the ADC Phillips 7164 module}}
+      * {{:wiki:Manual_Ortec_TAC_566.pdf|Manual for the TAC ORTEC 566 module}}
-The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800.
+  * Firmware FPGA Schematics
+      * {{:wiki:Usbtrig.pdf|Trigger module firmware (ULM LeCroy 2367 )}}
+      * {{:wiki:Stamp64.pdf|Time stamping firmware (XLM72)}}
+      * {{:wiki:Crdc5v.pdf|CRDC readout firmware (XLM72V)}}
-===== Busy circuit =====
-As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The global busy signal is formed by a logical OR of all busy signals. To eliminate delays caused by the cables routing the individual signals, the S800 trigger uses local latches that are set by the trigger signal and reset by the individual end-of-event signals. The length of the global busy is then determined by the slowest readout sequence.
-The busy circuit following the generation of raw triggers is mainly composed of a latch that is set by the "Raw trigger" signal, and cleared by the falling edge of the OR of the individual busy signals (Busy inputs) coming from individual crate controllers or other data acquisition systems. This way the "Live trigger" signal stays true as long as the longest busy signal. The "Live trigger" signal is therefore a "global busy" signal as well. In addition, the same busy signals of individual crate controllers or other data acquisition system are used to veto the "Raw trigger" signal and prevent the generation of a live trigger. This takes care of situations where separate triggers are generated for some of the crate controllers or other data acquisition systems (such as scaler readout sequences), during which no event readout sequence should be started.
-===== Gate generation =====
-All digitizer gates and start signals are derived from the live trigger signal, with the exception of the QDC gate which is directly generated from the S800 source signal. The reason is to avoid long analog delays on the scintillator signals. A fast clear circuit is provided to clear the QDC if no valid trigger was generated.
-Inspect channels
-A set of four inspect channels are patched out to the Data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit.
-===== VME time stamp XLM72 module =====
-The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. This section describes the firmware used to configure this module into a 64 bit latched time stamp module. The inputs are the following:
-E1: time stamp clock input
-E2: latch input
-E3: clear input
-The clear can be done via software as well, and is usually done that way.
-The schematics of the firmware can be is available.  The Verilog code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME bus is also available.
-Configuration for S800 in tandem with other detectors
-In its standard configuration, the S800 data acquisition uses one CAMAC crate and one VME crate only. The CC-USB and VM-USB crate controller modules performing the readout are connected to the latches number 1 and 2 of the trigger module, respectively. Each crate controller is configured to output their busy and end-of-event signals on their available NIM outputs, which are then connected to the appropriate inputs on the trigger module.
-To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following:
-•	Raw trigger from external detector to Secondary source
-•	Live trigger from S800 trigger to external data acquisition (trigger input)
-•	Time stamp clock from S800 trigger to external data acquisition (time stamp input)
-•	End-of-event from external data acquisition to S800 trigger
-•	Busy from external data acquisition to S800 trigger
-Time stamping scheme=================
-The S800 trigger provides a vetoed 10 MHz clock signal used for time stamping (an external clock can also be used). The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset, typically during the begin sequences of the controllers or data acquisitions. The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme ensures that all time stamp counters are synchronized.
-Busy scheme
-As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The global busy signal is formed by a logical OR of all busy signals. To eliminate delays caused by the cables routing the individual signals, the S800 trigger uses local latches that are set by the trigger signal and reset by the individual end-of-event signals. The length of the global busy is then determined by the slowest readout sequence.

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