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====== Electronics ====== | ====== Electronics ====== | ||
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+ | * Crate Map | ||
+ | * Trigger | ||
+ | * Schematics: | ||
+ | * Trigger Electronics Diagram | ||
+ | * Fast Timing Electronics Diagram | ||
+ | * CRDC Electronics Diagram | ||
+ | * Ion Chamber Electronics Diagram | ||
+ | * Tracking PPAC Electronics Diagram | ||
+ | * All Electronic Diagrams in one document | ||
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===== Schematics ===== | ===== Schematics ===== | ||
- | The trigger logic of the S800 is implemented in a FPGA driven module. Apart from reducing the cabling and number of modules, this module allows the user to remotely control and inspect trigger signals, even while beam is present in the vault. In addition, the trigger | + | The trigger logic of the S800 is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx |
- | The FPGA module uses the LeCroy 2367 Universal Logic Module (ULM) to implement the S800 trigger logic by means of its XC4000E Xilinx FPGA. The main purpose of the trigger is to implement a coincidence between the S800 focal plane and a secondary detector principally located at the target location. | + | The main purpose of the trigger is to implement a coincidence between the S800 focal plane and a secondary detector principally located at the target location. The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. |
+ | {{: | ||
- | The S800 trigger | + | The two main trigger |
- | + | ||
- | {{: | + | |
- | The two main trigger sources are labeled " | ||
The S800 trigger source comes from the fast timing scintillator [[Detectors# | The S800 trigger source comes from the fast timing scintillator [[Detectors# | ||
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===== Trigger Box ===== | ===== Trigger Box ===== | ||
- | In addition to the singles and coincidence triggers, two separate | + | In addition to the singles and coincidence triggers, two separate |
+ | |||
+ | Since more than one trigger source | ||
+ | |||
===== Time stamping ===== | ===== Time stamping ===== | ||
- | As the S800 USB-based data acquisition uses independent crate controllers, | + | Because |
- | The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. | + | The time stamp module is implemented in a VME XLM72 (SpartanXL) FPGA. The schematics of the firmware is available. |
+ | The inputs are the following: | ||
+ | * E1: time stamp clock input | ||
+ | * E2: latch input | ||
+ | * E3: clear input | ||
+ | |||
+ | The clear can be done via software as well, and is usually done that way. | ||
The trigger module FPGA configuration contains a 64 bit counter which is latched by the "Live trigger" | The trigger module FPGA configuration contains a 64 bit counter which is latched by the "Live trigger" | ||
- | The clock signal is released when the " | + | The clock signal is released when the " |
The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. | ||
- | |||
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- | ===== VME time stamp XLM72 module ===== | + | ===== Configuration for S800 in tandem with other detectors |
- | The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. This section describes the firmware used to configure this module into a 64 bit latched time stamp module. The inputs are the following: | + | |
- | + | ||
- | E1: time stamp clock input | + | |
- | E2: latch input | + | |
- | E3: clear input | + | |
- | The clear can be done via software as well, and is usually done that way. | + | |
- | + | ||
- | The schematics of the firmware can be is available. | + | |
- | + | ||
- | + | ||
- | + | ||
- | Configuration for S800 in tandem with other detectors | + | |
In its standard configuration, | In its standard configuration, | ||
To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following: | To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following: | ||
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- | Time stamping scheme================= | ||
- | The S800 trigger provides a vetoed 10 MHz clock signal used for time stamping (an external clock can also be used). The clock is inhibited by a " | ||
- | Busy scheme | ||
- | As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The global busy signal is formed by a logical OR of all busy signals. To eliminate delays caused by the cables routing the individual signals, the S800 trigger uses local latches that are set by the trigger signal and reset by the individual end-of-event signals. The length of the global busy is then determined by the slowest readout sequence. | ||
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+ | Begin sequence | ||
+ | |||
+ | The internal " | ||
+ | |||
+ | The data acquisition begin sequence of the trigger module is the following: | ||
+ | reset time stamp counter to 0 | ||
+ | reset trigger register to 0 | ||
+ | after all modules in all crates have been initialized, | ||
+ | after a preset delay of 200 to 300 microseconds, | ||
+ | |||
+ | The last step of the begin sequence allows enough time for the CCUSB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the " | ||
+ | |||
+ | Scalers and dead time | ||
+ | |||
+ | The " | ||
+ | |||
+ | In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger. | ||
+ | |||
+ | Trigger module | ||
+ | |||
+ | The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/ | ||
+ | |||
+ | CAMAC commands | ||
+ | |||
+ | The following table lists the CAMAC codes recognized by the trigger module and their signification. | ||
+ | |||
+ | F A Direction | ||
+ | 0 0 Read 16 0 Write S800 Gate & Delay (delay) | ||
+ | 0 1 Read 16 1 Write S800 Gate & Delay (width) | ||
+ | 0 2 Read 16 2 Write Secondary Gate & Delay (delay) | ||
+ | 0 3 Read 16 3 Write Secondary Gate & Delay (width) | ||
+ | 0 4 Read 16 4 Write S800 Delay (delay) | ||
+ | 0 5 Read 16 5 Write Coincidence Gate (width) | ||
+ | 0 6 Read 16 6 Write Secondary Delay (delay) | ||
+ | 0 7 Read 16 7 Write Bypasses (bit pattern) | ||
+ | 0 8 Read 16 8 Write S800 Downscaler (factor) | ||
+ | 0 9 Read 16 9 Write Secondary Downscaler (factor) | ||
+ | 0 10 Read 16 10 Write Trigger Box (bit pattern) | ||
+ | 0 11 Read 16 11 Write Go signal (bit) | ||
+ | 0 12 Read 16 12 Write External Time Stamp Clock (bit 0) | ||
+ | and External Time Stamp Latch (bit 1) | ||
+ | |||
+ | 0 14 Read | ||
+ | 0 15 Read | ||
+ | 1 0 Read 17 0 Write Inspect Channel 1 (wire) | ||
+ | 1 1 Read 17 1 Write Inspect Channel 2 (wire) | ||
+ | 1 2 Read 17 2 Write Inspect Channel 3 (wire) | ||
+ | 1 3 Read 17 3 Write Inspect Channel 4 (wire) | ||
+ | 2 0 Read 18 0 Write ADC Gate (width) | ||
+ | 2 1 Read 18 1 Write QDC Gate (width) | ||
+ | 2 2 Read 18 2 Write TDC Gate (width) | ||
+ | 2 3 Read 18 3 Write Coincidence Register Gate (width) | ||
+ | 3 0 Read | ||
+ | 3 1 Read Time Stamp (bits 0-15) | ||
+ | 3 2 Read Time Stamp (bits 16-31) | ||
+ | 3 3 Read Time Stamp (bits 32-47) | ||
+ | 3 4 Read Time Stamp (bits 48-63) | ||
+ | |||
+ | Inputs and outputs | ||
+ | |||
+ | The following table lists the inputs and outputs to/from the trigger module and their assignment. | ||
+ | |||
+ | Pin Assignment | ||
+ | A1 (in) S800 source | ||
+ | A2 (in) Secondary source | ||
+ | A3 (in) External 1 source | ||
+ | A4 (in) External 2 source | ||
+ | A5 (in) Clear busy B5 (out) TDC start C5 (in) Busy 5 D5 (out) S800 trigger | ||
+ | A6 (in) Clear module | ||
+ | A7 (in) Gretina sync B7 (out) C7 (in) Busy 7 D7 (out) External 1 trigger | ||
+ | A8 (in) Time stamp clock B8 (out) Live trigger | ||
+ | B9 (out) Inspect 1 C9 (out) Time stamp clock D9 (out) Secondary trigger | ||
+ | B10 (out) Inspect 2 C10 (out) Time stamp latch D10 (out) Raw trigger | ||
+ | B11 (out) Inspect 3 C11 (out) D11 (out) Live trigger | ||
+ | B12 (out) Inspect 4 C12 (out) D12 (out) Raw pulser | ||
+ | B13 (out) Fast clear C13 (out) D13 (out) Live pulser | ||
+ | B14 (out) C14 (out) D14 (out) Fast clear | ||
+ | B15 (out) Go C15 (out) D15 (out) 10 Hz | ||
+ | B16 (out) Time stamp clock C16 (out) D16 (out) 1 Hz | ||
+ | |||
+ | FPGA firmware | ||
+ | |||
+ | The firmware of the trigger module is shown in the following files. The PDF file contains the schematic sheets, used for most of the design. The Verilog file contains the block dealing with CAMAC communications. | ||
+ | |||
+ | File containing the schematics: File: | ||
+ | |||
+ | Below is the Verilog code used in the configuration for the INTERNAL module: | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | ) ; | ||
+ | |||
+ | input N ; | ||
+ | input S1 ; | ||
+ | input S2 ; | ||
+ | input Clock ; | ||
+ | input [4:0] F ; | ||
+ | input [3:0] A ; | ||
+ | input [23:0] Data_in ; | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | input [4:0] Register; | ||
+ | | ||
+ | | ||
+ | | ||
+ | input [63:0] TimeStamp; | ||
+ | | ||
+ | | ||
+ | |||
+ | // add your declarations here | ||
+ | reg X; | ||
+ | reg Q; | ||
+ | reg DriveRead ; | ||
+ | reg ClearModule; | ||
+ | reg ClearRegister; | ||
+ | reg Go; | ||
+ | reg [1:0] Select; | ||
+ | reg SyncEnable; | ||
+ | reg [23:0] Data_out ; | ||
+ | reg [7:0] S800Delay; | ||
+ | reg [7:0] S800Width ; | ||
+ | reg [7:0] SecondaryDelay; | ||
+ | reg [7:0] SecondaryWidth ; | ||
+ | reg [7:0] S800TimingDelay; | ||
+ | reg [7:0] CoincTimingWidth ; | ||
+ | reg [7:0] SecondaryTimingDelay ; | ||
+ | reg [4:0] Bypasses ; | ||
+ | reg [9:0] S800Factor ; | ||
+ | reg [9:0] SecondaryFactor ; | ||
+ | reg [4:0] TriggerBox ; | ||
+ | reg [7:0] ADCGate ; | ||
+ | reg [7:0] QDCGate ; | ||
+ | reg [7:0] TDCStart ; | ||
+ | reg [7:0] Coincidence ; | ||
+ | reg [4:0] Inspect1 ; | ||
+ | reg [4:0] Inspect2 ; | ||
+ | reg [4:0] Inspect3 ; | ||
+ | reg [4:0] Inspect4 ; | ||
+ | |||
+ | // add your code here | ||
+ | | ||
+ | if (N) begin | ||
+ | case (F) | ||
+ | | ||
+ | case (A) | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | end // F=0 | ||
+ | |||
+ | | ||
+ | case (A) | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | end // F=1 | ||
+ | |||
+ | | ||
+ | case (A) | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | end // F=2 | ||
+ | |||
+ | | ||
+ | case (A) | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | end // F=3 | ||
+ | |||
+ | | ||
+ | end // F=9 | ||
+ | |||
+ | | ||
+ | if (S1) begin | ||
+ | case (A) | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | end // S1=1 | ||
+ | end // F=16 | ||
+ | |||
+ | | ||
+ | if (S1) begin | ||
+ | case (A) | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | end // S1=1 | ||
+ | end // F=17 | ||
+ | |||
+ | | ||
+ | if (S1) begin | ||
+ | case (A) | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | end // S1=1 | ||
+ | end // F=18 | ||
+ | | ||
+ | | ||
+ | end //N=1 | ||
+ | |||
+ | end // always Clock | ||
+ | |||
+ | | ||
+ | if (N) begin | ||
+ | |||
+ | case (F) | ||
+ | |||
+ | | ||
+ | X = 1'b1; | ||
+ | Q = 1'b1; | ||
+ | | ||
+ | | ||
+ | | ||
+ | end // F=0 | ||
+ | |||
+ | | ||
+ | X = 1'b1; | ||
+ | Q = 1'b1; | ||
+ | | ||
+ | | ||
+ | | ||
+ | end // F=1 | ||
+ | |||
+ | | ||
+ | X = 1'b1; | ||
+ | Q = 1'b1; | ||
+ | | ||
+ | | ||
+ | | ||
+ | end // F=2 | ||
+ | |||
+ | | ||
+ | X = 1'b1; | ||
+ | Q = 1'b1; | ||
+ | | ||
+ | | ||
+ | | ||
+ | end // F=3 | ||
+ | |||
+ | | ||
+ | X = 1'b1; | ||
+ | Q = 1'b1; | ||
+ | | ||
+ | | ||
+ | | ||
+ | end // F=9 | ||
+ | |||
+ | | ||
+ | X = 1'b1; | ||
+ | Q = 1'b1; | ||
+ | | ||
+ | | ||
+ | | ||
+ | end // F=9 | ||
+ | |||
+ | | ||
+ | X = 1'b1; | ||
+ | Q = 1'b1; | ||
+ | | ||
+ | | ||
+ | | ||
+ | end // F=16 | ||
+ | |||
+ | | ||
+ | X = 1'b1; | ||
+ | Q = 1'b1; | ||
+ | | ||
+ | | ||
+ | | ||
+ | end // F=17 | ||
+ | |||
+ | | ||
+ | X = 1'b1; | ||
+ | Q = 1'b1; | ||
+ | | ||
+ | | ||
+ | | ||
+ | end // F=18 | ||
+ | |||
+ | | ||
+ | | ||
+ | | ||
+ | | ||
+ | X = 1'b0; | ||
+ | Q = 1'b0; | ||
+ | end // default F | ||
+ | |||
+ | | ||
+ | end // if (N) | ||
+ | |||
+ | else begin | ||
+ | | ||
+ | | ||
+ | | ||
+ | X = 1'b0; | ||
+ | Q = 1'b0; | ||
+ | end // if (!N) | ||
+ | end // always N or S1 or A or F | ||
+ | |||
+ | | ||
+ | |||
+ | | ||
+ | |||
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