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electronics [2013/10/24 10:08]
pereira |
electronics [2013/10/24 11:15]
pereira |
| ====== Electronics ====== | ====== Electronics ====== |
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| | * [[https://groups.nscl.msu.edu/opdevtech/new-wiki/index.php/Crate_Map|Crate Map]] |
| | * [[https://groups.nscl.msu.edu/opdevtech/new-wiki/index.php/Trigger|Trigger]] |
| | * Schematics: |
| | * [[https://groups.nscl.msu.edu/s800/Technical/Electronics/Electronics_frameset.htm|Trigger Electronics Diagram]] |
| | * [[https://groups.nscl.msu.edu/s800/Technical/Electronics/Electronics_frameset.htm|Fast Timing Electronics Diagram]] |
| | * [[https://groups.nscl.msu.edu/s800/Technical/Electronics/Electronics_frameset.htm|CRDC Electronics Diagram]] |
| | * [[https://groups.nscl.msu.edu/s800/Technical/Electronics/Electronics_frameset.htm|Ion Chamber Electronics Diagram]] |
| | * [[https://groups.nscl.msu.edu/s800/Technical/Electronics/Electronics_frameset.htm|Tracking PPAC Electronics Diagram]] |
| | * [[https://groups.nscl.msu.edu/s800/Technical/Electronics/Electronics_frameset.htm|All Electronic Diagrams in one document]] |
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| ===== Schematics ===== | ===== Schematics ===== |
| The trigger logic of the S800 is implemented in a FPGA driven module. Apart from reducing the cabling and number of modules, this module allows the user to remotely control and inspect trigger signals, even while beam is present in the vault. In addition, the trigger configuration can be saved and restored at any time. | The trigger logic of the S800 is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. Apart from reducing the cabling and number of modules, this module allows the user to remotely control and inspect trigger signals, even while beam is present in the vault. In addition, the configuration can be saved and restored at any time. |
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| The FPGA module uses the LeCroy 2367 Universal Logic Module (ULM) to implement the S800 trigger logic by means of its XC4000E Xilinx FPGA. The main purpose of the trigger is to implement a coincidence between the S800 focal plane and a secondary detector principally located at the target location. | The main purpose of the trigger is to implement a coincidence between the S800 focal plane and a secondary detector principally located at the target location. The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. |
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| The S800 trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | |
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| {{:wiki:800px-TriggerGUI.png?700|Layout of the S800}} | {{:wiki:800px-TriggerGUI.png?700|Layout of the S800}} |
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| ===== Trigger Box ===== | ===== Trigger Box ===== |
| In addition to the singles and coincidence triggers, two separate inputs called "External 1" and "External 2" can be used as trigger sources. All sources can be independently selected by selecting the appropriate check box in the trigger box (see figure above), which is a logical OR of all five inputs. This means in case more than one trigger source is selected, it is possible that more than one pulse is generated at the output, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" output of the trigger box may generate two pulses for a single event. A scaler connected to the "Raw trigger" output will therefore not reflect the true number of events. For this reason scalers are also connected to individual inputs of the trigger box. A trigger register word (bit pattern) is written at each occurrence of a live trigger signal. This word is the first being read out from the trigger module, prior to the time stamp. | In addition to the singles and coincidence triggers, two separate trigger sources labeled "External 1" and "External 2" can be used. The various sources can be selected from the trigger box to define the raw trigger, which is then sent to a third AND gate for computer busy rejection. The busy latch (on the middle) is set by the raw trigger after a 50ns delay, and prevents subsequent events to be accepted. It is reset by the computer once the current event has been processed. The live trigger signal is fed to gate generators used to generate appropriate gates for the ADCs, QDCs, TDCs and an eventual coincidence register. Note that the trigger box contains its own coincidence register for which the input signals are delayed by 50ns, and the gate width is set by the coincidence gate generator. The request event signal is latched before being sent to the computer. |
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| | Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" output of the trigger box may generate two pulses for a single event. A scaler connected to the "Raw trigger" output will therefore not reflect the true number of events. For this reason scalers are also connected to individual inputs of the trigger box. A trigger register word (bit pattern) is written at each occurrence of a live trigger signal. This word is the first being read out from the trigger module, prior to the time stamp. |
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| ===== Time stamping ===== | ===== Time stamping ===== |
| As the S800 USB-based data acquisition uses independent crate controllers, time stamping between the crates is required in order to synchronize the events properly. The same synchronization scheme can be used when coupling external data acquisition systems to the S800. | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward. |
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| The time stamp module is implemented in a VME XLM72 (SpartanXL) FPGA. The schematics of the firmware is available. The Verilog code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME bus is also available. | The time stamp module is implemented in a VME XLM72 (SpartanXL) FPGA. The schematics of the firmware is available. The Verilog code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME bus is also available. |
