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--- electronics [2013/10/24 10:21]
pereira
+++ electronics [2013/12/10 15:37]
pereira
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 ====== Electronics ======
+  * [[Electronics#Crate Configuration|Crate Configuration]]
+  * [[Electronics#Inventory Modules|Inventory Modules]]
+  * [[Electronics#Electronic Diagrams|Electronic Diagrams]]
+  * [[Electronics#Trigger|Trigger]]
-===== General description =====
-The trigger of the S800 offers the possibility to combine the S800 trigger with triggers from other detectors or arrays in order to form coincidences. This is often a mandatory requirement when the trigger rate of the S800 alone (S800 singles) is too high for the data acquisition and the resulting dead time is prohibitive.
-Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward.
+===== Crate Configuration =====
+A preliminary scheme of the crate configuration (in progress) can be found {{:wiki:s800electronicstcrateconfiguration2.pdf|here}}.
+===== Inventory Modules =====
+In progress.
-===== Schematics =====
-The trigger logic of the S800 is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. Apart from reducing the cabling and number of modules, this module allows the user to remotely control and inspect trigger signals, even while beam is present in the vault. In addition, the configuration can be saved and restored at any time.
-The main purpose of the trigger is to implement a coincidence between the S800 focal plane and a secondary detector principally located at the target location. The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below.
+===== Electronic Diagrams =====
+  * {{:wiki:s800electronicstschematics_to20131125.pdf|Main Electronic Diagram}}
+  * {{:wiki:crdcdiagram.pdf|CRDC Schematic Electronic Diagram}}
+  * {{:wiki:ionchamber.pdf|Ion Chamber Schematic Electronics Diagram}}
+  * {{:wiki:tppacelectronics.pdf|Tracking PPAC Schematic Electronics Diagram}}
+  * {{:wiki:trigger_scheme.pdf|Trigger Schematic Electronics Diagram}}
+  * {{:wiki:fasttimimg.pdf|Fast Timing Schematic Electronics Diagram}}
+===== Trigger =====
+The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors#Plastic scintillators|E1]] and a secondary detector principally located at the target location. This coincidence is often a mandatory requirement when the trigger rate of the S800 alone (S800 singles) is too high for the data acquisition and the resulting dead time is prohibitive.
+The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. The main motivations for implementing the trigger logic in an FPGA driven module are the following:
+  - Simplify cabling and setup of the trigger
+  - Reduce the number of modules used to implement the trigger
+  - Ability to remotely control and inspect trigger signals
+  - Ability to save and restore the trigger configuration
+  - Direct visualization of the trigger logic and configuration
+Probably the most appealing feature of this module is the possibility to remotely control the trigger timing and configuration while beam is present in the vault, since most experiments are nowadays locating their electronics close to the detectors.
+===== General description =====
+The S800 trigger source comes from the fast timing scintillator [[Detectors#Plastic scintillators|E1]] located in the focal plane. This trigger can be combined with triggers from other detectors or arrays in order to form coincidences. This is often a mandatory requirement when the trigger rate of the S800 alone (S800 singles) is too high for the data acquisition and the resulting dead time is prohibitive.
-{{:wiki:800px-TriggerGUI.png?700|Layout of the S800}}
-The two main trigger sources are labeled "S800" and "Secondary" in the GUI. Each source is routed to a gate and delay generator before forming a coincidence in the following AND gate. The AND signal is then widened before being ANDed with the delayed S800 source signal. The purpose of the second AND gate is to reset the timing of the coincidence to the S800 timing. This is necessary in case the Secondary detector has a slow timing and large jitter (Germanium detectors for instance). Single triggers from each trigger source are also available in a second branch, after going through a delay generator followed by a downscaler (used to take a reduced number of events from the trigger sources). Note that each gate and delay generator can be bypassed.
-The S800 trigger source comes from the fast timing scintillator [[Detectors#Plastic scintillators|E1]] located in the focal plane, and always provides the reference time for the [[Detectors#Cathode Readout Drift Chambers (CRDC)|CRDCs]] as well as time-of-flight measurements. Note that because the FPGA uses a 40 MHz internal clock the time reference of the signals in the trigger circuit are set the phase of that clock, and therefore jitter by 25 ns with respect to the source signals. This jitter is measured with a TDC and can be subtracted to the time measurements to recover the timing relative to the source signals.
 ===== Trigger Box =====
-In addition to the singles and coincidence triggers, two separate inputs called "External 1" and "External 2" can be used as trigger sources. All sources can be independently selected by selecting the appropriate check box in the trigger box (see figure above), which is a logical OR of all five inputs. This means in case more than one trigger source is selected, it is possible that more than one pulse is generated at the output, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" output of the trigger box may generate two pulses for a single event. A scaler connected to the "Raw trigger" output will therefore not reflect the true number of events. For this reason scalers are also connected to individual inputs of the trigger box. A trigger register word (bit pattern) is written at each occurrence of a live trigger signal. This word is the first being read out from the trigger module, prior to the time stamp.
+The main purpose of the trigger is to implement a coincidence between the S800 focal plane and a secondary detector principally located at the target location. The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. One of the main advantages of this module are:
+  -  The reduction of cabling and number of modules involved in the implementation of the trigger logic.
+  -  The possibility to remotely control and inspect trigger signals, even while beam is present in the vault.
+  -  The possibility to save and restore the trigger configuration at any time.
+The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below.
+{{:wiki:TriggerGUI.png?900|Trigger schematics of the S800}}
+The two main trigger sources are labeled "S800" and "Secondary" in the GUI. Each source is routed to a gate and delay generator before forming a coincidence in the following AND gate. The AND signal is then widened before being ANDed with the delayed S800 source signal. The purpose of the second AND gate is to reset the timing of the coincidence to the S800 timing. This is necessary in case the secondary detector has a slow timing and large jitter (Germanium detectors for instance). Single triggers from each trigger source are also available in a second branch, after going through a delay generator followed by a downscaler (used to take a reduced number of events from the trigger sources). Note that each gate and delay generator can be bypassed.
+In addition to the singles and coincidence triggers, two separate trigger sources labeled "External 1" and "External 2" can be used. The various sources can be selected from the trigger box to define the raw trigger, which is then sent to a third AND gate for computer busy rejection. The busy latch (on the middle) is set by the raw trigger after a 50 ns delay, and prevents subsequent events to be accepted. It is reset by the computer once the current event has been processed. The live trigger signal feeds several gate generators which provide appropriate gates for the ADCs, QDCs, TDCs and an eventual coincidence register. Note that the trigger box contains its own coincidence register for which the input signals are delayed by 50 ns, and the gate width is set by the coincidence gate generator. The request event signal is latched before being sent to the computer.
+Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" output of the trigger box may generate two pulses for a single event. A scaler connected to the "Raw trigger" output will therefore not reflect the true number of events. For this reason scalers are also connected to individual inputs of the trigger box. A trigger register word (bit pattern) is written at each occurrence of a live trigger signal. This word is the first being read out from the trigger module, prior to the time stamp.
+The S800 trigger from the [[Detectors#Plastic scintillators|E1 scintillator]] provides the reference time for the [[Detectors#Cathode Readout Drift Chambers (CRDC)|CRDCs]] as well as time-of-flight measurements. Note that because the FPGA uses a 40 MHz internal clock, the time reference of the signals in the trigger circuit are set the phase of that clock, and therefore jitter by 25 ns with respect to the source signals. This jitter is measured with a TDC and can be subtracted to the time measurements to recover the timing relative to the source signals.
 ===== Time stamping =====
 Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward.
-The time stamp module is implemented in a VME XLM72 (SpartanXL) FPGA. The schematics of the firmware is available.  The Verilog code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME bus is also available.
+The time stamp module is implemented in a VME XLM72 (SpartanXL) FPGA. The schematics of the firmware is available here
+[[{{:wiki:Stamp64.pdf}}|here]]
+.  The Verilog code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME bus is also available.
 The inputs are the following:
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