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--- electronics [2013/10/24 10:49]
pereira
+++ electronics [2013/10/31 09:36]
pereira
@@ Line 9: / Line 9: @@
-===== Schematics =====
+===== Trigger Box =====
-The trigger logic of the S800 is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. Apart from reducing the cabling and number of modules, this module allows the user to remotely control and inspect trigger signals, even while beam is present in the vault. In addition, the configuration can be saved and restored at any time.
+The main purpose of the trigger is to implement a coincidence between the S800 focal plane and a secondary detector principally located at the target location. The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. One of the main advantages of this module are:
-The main purpose of the trigger is to implement a coincidence between the S800 focal plane and a secondary detector principally located at the target location. The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below.
+  -  The reduction of cabling and number of modules involved in the implementation of the trigger logic.
+  -  The possibility to remotely control and inspect trigger signals, even while beam is present in the vault.
+  -  The possibility to save and restore the trigger configuration at any time.
+The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below.
 {{:wiki:800px-TriggerGUI.png?700|Layout of the S800}}
-The two main trigger sources are labeled "S800" and "Secondary" in the GUI. Each source is routed to a gate and delay generator before forming a coincidence in the following AND gate. The AND signal is then widened before being ANDed with the delayed S800 source signal. The purpose of the second AND gate is to reset the timing of the coincidence to the S800 timing. This is necessary in case the Secondary detector has a slow timing and large jitter (Germanium detectors for instance). Single triggers from each trigger source are also available in a second branch, after going through a delay generator followed by a downscaler (used to take a reduced number of events from the trigger sources). Note that each gate and delay generator can be bypassed.
+The two main trigger sources are labeled "S800" and "Secondary" in the GUI. Each source is routed to a gate and delay generator before forming a coincidence in the following AND gate. The AND signal is then widened before being ANDed with the delayed S800 source signal. The purpose of the second AND gate is to reset the timing of the coincidence to the S800 timing. This is necessary in case the secondary detector has a slow timing and large jitter (Germanium detectors for instance). Single triggers from each trigger source are also available in a second branch, after going through a delay generator followed by a downscaler (used to take a reduced number of events from the trigger sources). Note that each gate and delay generator can be bypassed.
+In addition to the singles and coincidence triggers, two separate trigger sources labeled "External 1" and "External 2" can be used. The various sources can be selected from the trigger box to define the raw trigger, which is then sent to a third AND gate for computer busy rejection. The busy latch (on the middle) is set by the raw trigger after a 50 ns delay, and prevents subsequent events to be accepted. It is reset by the computer once the current event has been processed. The live trigger signal is fed to gate generators which provides appropriate gates for the ADCs, QDCs, TDCs and an eventual coincidence register. Note that the trigger box contains its own coincidence register for which the input signals are delayed by 50 ns, and the gate width is set by the coincidence gate generator. The request event signal is latched before being sent to the computer.
-The S800 trigger source comes from the fast timing scintillator [[Detectors#Plastic scintillators|E1]] located in the focal plane, and always provides the reference time for the [[Detectors#Cathode Readout Drift Chambers (CRDC)|CRDCs]] as well as time-of-flight measurements. Note that because the FPGA uses a 40 MHz internal clock the time reference of the signals in the trigger circuit are set the phase of that clock, and therefore jitter by 25 ns with respect to the source signals. This jitter is measured with a TDC and can be subtracted to the time measurements to recover the timing relative to the source signals.
+Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" output of the trigger box may generate two pulses for a single event. A scaler connected to the "Raw trigger" output will therefore not reflect the true number of events. For this reason scalers are also connected to individual inputs of the trigger box. A trigger register word (bit pattern) is written at each occurrence of a live trigger signal. This word is the first being read out from the trigger module, prior to the time stamp.
-===== Trigger Box =====
-In addition to the singles and coincidence triggers, two separate trigger sources labeled "External 1" and "External 2" can be used. The various sources can be selected from the trigger box to define the raw trigger, which is then sent to a third AND gate for computer busy rejection. The busy latch (on the middle) is set by the raw trigger after a 50ns delay, and prevents subsequent events to be accepted. It is reset by the computer once the current event has been processed. The live trigger signal is fed to gate generators used to generate appropriate gates for the ADCs, QDCs, TDCs and an eventual coincidence register. Note that the trigger box contains its own coincidence register for which the input signals are delayed by 50ns, and the gate width is set by the coincidence gate generator. The request event signal is latched before being sent to the computer.
-Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" output of the trigger box may generate two pulses for a single event. A scaler connected to the "Raw trigger" output will therefore not reflect the true number of events. For this reason scalers are also connected to individual inputs of the trigger box. A trigger register word (bit pattern) is written at each occurrence of a live trigger signal. This word is the first being read out from the trigger module, prior to the time stamp.
+The S800 trigger source comes from the fast timing scintillator [[Detectors#Plastic scintillators|E1]] located in the focal plane, and always provides the reference time for the [[Detectors#Cathode Readout Drift Chambers (CRDC)|CRDCs]] as well as time-of-flight measurements. Note that because the FPGA uses a 40 MHz internal clock, the time reference of the signals in the trigger circuit are set the phase of that clock, and therefore jitter by 25 ns with respect to the source signals. This jitter is measured with a TDC and can be subtracted to the time measurements to recover the timing relative to the source signals.
+===== Trigger Box =====

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