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electronics [2013/10/24 11:15]
pereira |
electronics [2013/10/31 09:26]
pereira |
| ====== Electronics ====== | ====== Electronics ====== |
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| * [[https://groups.nscl.msu.edu/opdevtech/new-wiki/index.php/Crate_Map|Crate Map]] | |
| * [[https://groups.nscl.msu.edu/opdevtech/new-wiki/index.php/Trigger|Trigger]] | |
| * Schematics: | |
| * [[https://groups.nscl.msu.edu/s800/Technical/Electronics/Electronics_frameset.htm|Trigger Electronics Diagram]] | |
| * [[https://groups.nscl.msu.edu/s800/Technical/Electronics/Electronics_frameset.htm|Fast Timing Electronics Diagram]] | |
| * [[https://groups.nscl.msu.edu/s800/Technical/Electronics/Electronics_frameset.htm|CRDC Electronics Diagram]] | |
| * [[https://groups.nscl.msu.edu/s800/Technical/Electronics/Electronics_frameset.htm|Ion Chamber Electronics Diagram]] | |
| * [[https://groups.nscl.msu.edu/s800/Technical/Electronics/Electronics_frameset.htm|Tracking PPAC Electronics Diagram]] | |
| * [[https://groups.nscl.msu.edu/s800/Technical/Electronics/Electronics_frameset.htm|All Electronic Diagrams in one document]] | |
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| ===== Schematics ===== | ===== Schematics ===== |
| The trigger logic of the S800 is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. Apart from reducing the cabling and number of modules, this module allows the user to remotely control and inspect trigger signals, even while beam is present in the vault. In addition, the configuration can be saved and restored at any time. | The main purpose of the trigger is to implement a coincidence between the S800 focal plane and a secondary detector principally located at the target location. The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. One of the main advantages of this module are: |
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| | - The reduction of cabling and number of modules involved in the implementation of the trigger logic. |
| | - The possibility to remotely control and inspect trigger signals, even while beam is present in the vault. |
| | - The possibility to save and restore the trigger configuration at any time. |
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| The main purpose of the trigger is to implement a coincidence between the S800 focal plane and a secondary detector principally located at the target location. The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. |
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| {{:wiki:800px-TriggerGUI.png?700|Layout of the S800}} | {{:wiki:800px-TriggerGUI.png?700|Layout of the S800}} |
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| The two main trigger sources are labeled "S800" and "Secondary" in the GUI. Each source is routed to a gate and delay generator before forming a coincidence in the following AND gate. The AND signal is then widened before being ANDed with the delayed S800 source signal. The purpose of the second AND gate is to reset the timing of the coincidence to the S800 timing. This is necessary in case the Secondary detector has a slow timing and large jitter (Germanium detectors for instance). Single triggers from each trigger source are also available in a second branch, after going through a delay generator followed by a downscaler (used to take a reduced number of events from the trigger sources). Note that each gate and delay generator can be bypassed. | The two main trigger sources are labeled "S800" and "Secondary" in the GUI. Each source is routed to a gate and delay generator before forming a coincidence in the following AND gate. The AND signal is then widened before being ANDed with the delayed S800 source signal. The purpose of the second AND gate is to reset the timing of the coincidence to the S800 timing. This is necessary in case the secondary detector has a slow timing and large jitter (Germanium detectors for instance). Single triggers from each trigger source are also available in a second branch, after going through a delay generator followed by a downscaler (used to take a reduced number of events from the trigger sources). Note that each gate and delay generator can be bypassed. |
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| The S800 trigger source comes from the fast timing scintillator [[Detectors#Plastic scintillators|E1]] located in the focal plane, and always provides the reference time for the [[Detectors#Cathode Readout Drift Chambers (CRDC)|CRDCs]] as well as time-of-flight measurements. Note that because the FPGA uses a 40 MHz internal clock the time reference of the signals in the trigger circuit are set the phase of that clock, and therefore jitter by 25 ns with respect to the source signals. This jitter is measured with a TDC and can be subtracted to the time measurements to recover the timing relative to the source signals. | The S800 trigger source comes from the fast timing scintillator [[Detectors#Plastic scintillators|E1]] located in the focal plane, and always provides the reference time for the [[Detectors#Cathode Readout Drift Chambers (CRDC)|CRDCs]] as well as time-of-flight measurements. Note that because the FPGA uses a 40 MHz internal clock, the time reference of the signals in the trigger circuit are set the phase of that clock, and therefore jitter by 25 ns with respect to the source signals. This jitter is measured with a TDC and can be subtracted to the time measurements to recover the timing relative to the source signals. |
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