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====== Electronics ====== | ====== Electronics ====== | ||
+ | * [[Electronics# | ||
+ | * [[Electronics# | ||
+ | * [[Electronics# | ||
+ | * [[Electronics# | ||
+ | * [[Trigger|ULM Trigger module]] | ||
+ | * [[Timing|Timing modules]] | ||
+ | * [[XLM Delay|XLM Delay module]] | ||
+ | | ||
+ | ===== Crate Configuration ===== | ||
- | ===== General description ===== | + | Most of the S800 electronics is installed in two racks inside |
- | The trigger | + | |
- | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward. | ||
- | ===== Trigger Box ===== | + | {{: |
- | The main purpose | + | |
- | - The reduction of cabling and number of modules involved in the implementation of the trigger logic. | ||
- | - The possibility to remotely control and inspect trigger signals, even while beam is present in the vault. | ||
- | - The possibility to save and restore the trigger configuration at any time. | ||
- | The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | ||
- | {{: | ||
- | The two main trigger sources are labeled " | ||
- | In addition to the singles and coincidence triggers, two separate trigger sources labeled " | + | === VME crate === |
+ | {{: | ||
- | Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" | ||
+ | === CAMAC crate === | ||
+ | {{: | ||
- | The S800 trigger source comes from the fast timing scintillator [[Detectors# | + | === NIM crate 1 === |
+ | {{:wiki:nim-crate1.jpg?450|NIM crate 1}} | ||
- | ===== Trigger Box ===== | + | === NIM crate 2 === |
+ | {{: | ||
+ | === NIM crate 3 === | ||
+ | {{: | ||
- | ===== Time stamping ===== | ||
- | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward. | ||
- | The time stamp module is implemented in a VME XLM72 (SpartanXL) FPGA. The schematics of the firmware is available. | + | === NIM crate 4 === |
+ | {{: | ||
- | The inputs are the following: | ||
- | * E1: time stamp clock input | + | ===== Inventory Modules ===== |
- | * E2: latch input | + | In progress. |
- | * E3: clear input | + | |
- | The clear can be done via software as well, and is usually done that way. | ||
- | The trigger module FPGA configuration contains a 64 bit counter which is latched by the "Live trigger" | + | ===== Electronic Diagrams ===== |
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
- | The clock signal is released when the " | ||
- | |||
- | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. | ||
- | ===== Busy circuit | + | ===== Documentation |
- | As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The global busy signal is formed by a logical OR of all busy signals. To eliminate delays caused by the cables routing the individual signals, the S800 trigger uses local latches that are set by the trigger signal and reset by the individual end-of-event signals. The length of the global busy is then determined by the slowest readout sequence. | + | |
- | The busy circuit following | + | * Manuals for electronic modules |
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * Firmware FPGA Schematics | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
- | ===== Gate generation ===== | ||
- | All digitizer gates and start signals are derived from the live trigger signal, with the exception of the QDC gate which is directly generated from the S800 source signal. The reason is to avoid long analog delays on the scintillator signals. A fast clear circuit is provided to clear the QDC if no valid trigger was generated. | ||
- | ===== Inspect channels | + | ===== Timing |
- | A set of four inspect channels | + | In a typical S800 experiment, there are different time-of-flight (ToF) measurements that can be used to identify |
+ | Although it is possible to measure the ToF between any pair of timing sources, there are three " | ||
- | ===== Configuration for S800 in tandem with other detectors ===== | + | Although |
- | In its standard configuration, | + | |
- | To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following: | + | |
- | • Raw trigger from external detector to Secondary source | + | |
- | • Live trigger from S800 trigger to external data acquisition | + | |
- | • Time stamp clock from S800 trigger to external data acquisition (time stamp input) | + | |
- | • End-of-event from external data acquisition to S800 trigger | + | |
- | • Busy from external data acquisition to S800 trigger | + | |
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- | Begin sequence | + | |
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- | The internal | + | |
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- | The data acquisition begin sequence of the trigger module | + | |
- | reset time stamp counter to 0 | + | |
- | reset trigger register to 0 | + | |
- | after all modules in all crates have been initialized, | + | |
- | after a preset delay of 200 to 300 microseconds, the " | + | |
- | + | ||
- | The last step of the begin sequence allows enough time for the CCUSB crate controller to switch | + | |
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- | Scalers and dead time | + | |
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- | The " | + | |
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- | In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger. | + | |
- | + | ||
- | Trigger module | + | |
- | + | ||
- | The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/ | + | |
- | + | ||
- | CAMAC commands | + | |
- | + | ||
- | The following table lists the CAMAC codes recognized by the trigger module and their signification. | + | |
- | + | ||
- | F A Direction | + | |
- | 0 0 Read 16 0 Write S800 Gate & Delay (delay) | + | |
- | 0 1 Read 16 1 Write S800 Gate & Delay (width) | + | |
- | 0 2 Read 16 2 Write Secondary Gate & Delay (delay) | + | |
- | 0 3 Read 16 3 Write Secondary Gate & Delay (width) | + | |
- | 0 4 Read 16 4 Write S800 Delay (delay) | + | |
- | 0 5 Read 16 5 Write Coincidence Gate (width) | + | |
- | 0 6 Read 16 6 Write Secondary Delay (delay) | + | |
- | 0 7 Read 16 7 Write Bypasses (bit pattern) | + | |
- | 0 8 Read 16 8 Write S800 Downscaler (factor) | + | |
- | 0 9 Read 16 9 Write Secondary Downscaler (factor) | + | |
- | 0 10 Read 16 10 Write Trigger Box (bit pattern) | + | |
- | 0 11 Read 16 11 Write Go signal (bit) | + | |
- | 0 12 Read 16 12 Write External Time Stamp Clock (bit 0) | + | |
- | and External Time Stamp Latch (bit 1) | + | |
- | 0 14 Read | + | Some important things to know about each of these modules: |
- | 0 15 Read | + | |
- | 1 0 Read 17 0 Write Inspect Channel 1 (wire) | + | |
- | 1 1 Read 17 1 Write Inspect Channel 2 (wire) | + | |
- | 1 2 Read 17 2 Write Inspect Channel 3 (wire) | + | |
- | 1 3 Read 17 3 Write Inspect Channel 4 (wire) | + | |
- | 2 0 Read 18 0 Write ADC Gate (width) | + | |
- | 2 1 Read 18 1 Write QDC Gate (width) | + | |
- | 2 2 Read 18 2 Write TDC Gate (width) | + | |
- | 2 3 Read 18 3 Write Coincidence Register Gate (width) | + | |
- | 3 0 Read | + | |
- | 3 1 Read Time Stamp (bits 0-15) | + | |
- | 3 2 Read Time Stamp (bits 16-31) | + | |
- | 3 3 Read Time Stamp (bits 32-47) | + | |
- | 3 4 Read Time Stamp (bits 48-63) | + | |
- | Inputs and outputs | ||
- | The following table lists the inputs | + | === MTDC === |
+ | * This module has multi-hit capabilities and better time resolution than the Phillips TDC and TACs. However, it is not yet in production mode | ||
+ | * Before getting into the MTDC, the OBJ, XFP, and E1 up signals go through a {{: | ||
+ | * The OBJ signal into the MCFD comes directly from the detector via S3 patch panel #94 | ||
+ | * The XFP detector signal is sent to a {{: | ||
+ | * The MTDC timing signals do not require external delay adjustments because the matching window is sufficiently wide | ||
+ | * SpecTcl calculates the OBJ-FP | ||
- | Pin Assignment | ||
- | A1 (in) S800 source | ||
- | A2 (in) Secondary source | ||
- | A3 (in) External 1 source | ||
- | A4 (in) External 2 source | ||
- | A5 (in) Clear busy B5 (out) TDC start C5 (in) Busy 5 D5 (out) S800 trigger | ||
- | A6 (in) Clear module | ||
- | A7 (in) Gretina sync B7 (out) C7 (in) Busy 7 D7 (out) External 1 trigger | ||
- | A8 (in) Time stamp clock B8 (out) Live trigger | ||
- | B9 (out) Inspect 1 C9 (out) Time stamp clock D9 (out) Secondary trigger | ||
- | B10 (out) Inspect 2 C10 (out) Time stamp latch D10 (out) Raw trigger | ||
- | B11 (out) Inspect 3 C11 (out) D11 (out) Live trigger | ||
- | B12 (out) Inspect 4 C12 (out) D12 (out) Raw pulser | ||
- | B13 (out) Fast clear C13 (out) D13 (out) Live pulser | ||
- | B14 (out) C14 (out) D14 (out) Fast clear | ||
- | B15 (out) Go C15 (out) D15 (out) 10 Hz | ||
- | B16 (out) Time stamp clock C16 (out) D16 (out) 1 Hz | ||
- | FPGA firmware | + | === Tennelec TACs === |
+ | * Unlike the MTDC and Phillips TDC, there is no TAC for the RF-FP ToF | ||
+ | * Before going to their corresponding TAC, the OBJ and XFP detector signals are sent to a {{: | ||
+ | * The OBJ output from the CANBERRA 454 CFD is sent to the stop of OBJ-FP TAC via patch panel #62 | ||
+ | * The XFP output from the CANBERRA 454 CFD is sent to the stop of XFP-FP TAC via patch panel #70 | ||
- | The firmware of the trigger module | + | === Phillips TDC === |
+ | * Before going to the TDC, the OBJ and XFP detector signals are sent to a {{: | ||
+ | * The TDC start is provided by the [[Trigger|ULM | ||
+ | * The OBJ output signal from the CANBERRA 454 CFD is delayed | ||
+ | * The XFP output signal from the CANBERRA 454 CFD is delayed with the low-noise delay boxes in data U6, and sent to the TDC via patch panel #66 | ||
+ | * SpecTcl calculates the OBJ-FP and XFP-FP ToFs by substracting the E1 up time (channel 8) to the OBJ time (channel 14) and the XFP time (channel 15) | ||
- | File containing the schematics: File: | ||
- | |||
- | Below is the Verilog code used in the configuration for the INTERNAL module: | ||
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- | ) ; | ||
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- | input N ; | ||
- | input S1 ; | ||
- | input S2 ; | ||
- | input Clock ; | ||
- | input [4:0] F ; | ||
- | input [3:0] A ; | ||
- | input [23:0] Data_in ; | ||
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- | input [4:0] Register; | ||
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- | input [63:0] TimeStamp; | ||
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- | |||
- | // add your declarations here | ||
- | reg X; | ||
- | reg Q; | ||
- | reg DriveRead ; | ||
- | reg ClearModule; | ||
- | reg ClearRegister; | ||
- | reg Go; | ||
- | reg [1:0] Select; | ||
- | reg SyncEnable; | ||
- | reg [23:0] Data_out ; | ||
- | reg [7:0] S800Delay; | ||
- | reg [7:0] S800Width ; | ||
- | reg [7:0] SecondaryDelay; | ||
- | reg [7:0] SecondaryWidth ; | ||
- | reg [7:0] S800TimingDelay; | ||
- | reg [7:0] CoincTimingWidth ; | ||
- | reg [7:0] SecondaryTimingDelay ; | ||
- | reg [4:0] Bypasses ; | ||
- | reg [9:0] S800Factor ; | ||
- | reg [9:0] SecondaryFactor ; | ||
- | reg [4:0] TriggerBox ; | ||
- | reg [7:0] ADCGate ; | ||
- | reg [7:0] QDCGate ; | ||
- | reg [7:0] TDCStart ; | ||
- | reg [7:0] Coincidence ; | ||
- | reg [4:0] Inspect1 ; | ||
- | reg [4:0] Inspect2 ; | ||
- | reg [4:0] Inspect3 ; | ||
- | reg [4:0] Inspect4 ; | ||
- | |||
- | // add your code here | ||
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- | if (N) begin | ||
- | case (F) | ||
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- | case (A) | ||
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- | end // F=0 | ||
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- | case (A) | ||
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- | end // F=1 | ||
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- | case (A) | ||
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- | end // F=2 | ||
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- | case (A) | ||
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- | end // F=3 | ||
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- | end // F=9 | ||
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- | if (S1) begin | ||
- | case (A) | ||
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- | end // S1=1 | ||
- | end // F=16 | ||
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- | if (S1) begin | ||
- | case (A) | ||
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- | end // S1=1 | ||
- | end // F=17 | ||
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- | if (S1) begin | ||
- | case (A) | ||
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- | end // S1=1 | ||
- | end // F=18 | ||
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- | end //N=1 | ||
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- | end // always Clock | ||
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- | if (N) begin | ||
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- | case (F) | ||
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- | X = 1'b1; | ||
- | Q = 1'b1; | ||
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- | end // F=0 | ||
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- | X = 1'b1; | ||
- | Q = 1'b1; | ||
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- | end // F=1 | ||
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- | X = 1'b1; | ||
- | Q = 1'b1; | ||
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- | end // F=2 | ||
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- | X = 1'b1; | ||
- | Q = 1'b1; | ||
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- | end // F=3 | ||
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- | X = 1'b1; | ||
- | Q = 1'b1; | ||
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- | end // F=9 | ||
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- | X = 1'b1; | ||
- | Q = 1'b1; | ||
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- | end // F=9 | ||
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- | X = 1'b1; | ||
- | Q = 1'b1; | ||
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- | end // F=16 | ||
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- | X = 1'b1; | ||
- | Q = 1'b1; | ||
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- | end // F=17 | ||
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- | X = 1'b1; | ||
- | Q = 1'b1; | ||
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- | end // F=18 | ||
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- | X = 1'b0; | ||
- | Q = 1'b0; | ||
- | end // default F | ||
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- | end // if (N) | ||
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- | else begin | ||
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- | X = 1'b0; | ||
- | Q = 1'b0; | ||
- | end // if (!N) | ||
- | end // always N or S1 or A or F | ||
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- | This page was last modified on 8 January 2013, at 22:16. | ||
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