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electronics [2013/11/19 07:30] pereira |
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====== Electronics ====== | ====== Electronics ====== | ||
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+ | * [[Electronics# | ||
+ | * [[Electronics# | ||
+ | * [[Electronics# | ||
+ | * [[Electronics# | ||
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+ | ===== Crate Configuration ===== | ||
+ | A preliminary scheme of the crate configuration (in progress) can be found {{: | ||
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+ | ===== Inventory Modules ===== | ||
+ | In progress. | ||
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+ | ===== Electronic Diagrams ===== | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
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+ | ===== Trigger ===== | ||
+ | The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors# | ||
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+ | The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. The main motivations for implementing the trigger logic in an FPGA driven module are the following: | ||
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+ | - Simplify cabling and setup of the trigger | ||
+ | - Reduce the number of modules used to implement the trigger | ||
+ | - Ability to remotely control and inspect trigger signals | ||
+ | - Ability to save and restore the trigger configuration | ||
+ | - Direct visualization of the trigger logic and configuration | ||
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+ | Probably the most appealing feature of this module is the possibility to remotely control the trigger timing and configuration while beam is present in the vault, since most experiments are nowadays locating their electronics close to the detectors. | ||
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The S800 trigger source comes from the fast timing scintillator [[Detectors# | The S800 trigger source comes from the fast timing scintillator [[Detectors# | ||
- | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward. | + | |
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The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | ||
- | {{:wiki:800px-TriggerGUI.png? | + | {{: |
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The two main trigger sources are labeled " | The two main trigger sources are labeled " | ||
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Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward. | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward. | ||
- | The time stamp module is implemented in a VME XLM72 (SpartanXL) FPGA. The schematics of the firmware is available. | + | The time stamp module is implemented in a VME XLM72 (SpartanXL) FPGA. The schematics of the firmware is available |
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+ | [[{{: | ||
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+ | . The Verilog code of the REGISTERS module of the FPGA configuration, | ||
The inputs are the following: | The inputs are the following: | ||
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