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electronics [2013/11/19 07:33] pereira |
electronics [2013/12/10 15:24] pereira |
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====== Electronics ====== | ====== Electronics ====== | ||
+ | * [[Electronics# | ||
+ | * [[Electronics# | ||
+ | * [[Electronics# | ||
+ | * [[Electronics# | ||
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+ | ===== Crate Configuration ===== | ||
+ | A preliminary scheme of the crate configuration (in progress) can be found {{: | ||
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+ | ===== Inventory Modules ===== | ||
+ | In progress. | ||
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+ | ===== Electronic Diagrams ===== | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
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+ | ===== Trigger ===== | ||
===== General description ===== | ===== General description ===== | ||
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The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | ||
- | {{: | + | {{: |
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The two main trigger sources are labeled " | The two main trigger sources are labeled " | ||
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Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward. | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward. | ||
- | The time stamp module is implemented in a VME XLM72 (SpartanXL) FPGA. The schematics of the firmware is available. | + | The time stamp module is implemented in a VME XLM72 (SpartanXL) FPGA. The schematics of the firmware is available |
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+ | [[{{: | ||
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+ | . The Verilog code of the REGISTERS module of the FPGA configuration, | ||
The inputs are the following: | The inputs are the following: | ||
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