Differences

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--- electronics [2013/11/19 07:38]
pereira
+++ electronics [2013/11/19 07:57]
pereira
@@ Line 18: / Line 18: @@
 The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below.
-{{:wiki:TriggerGUI.png?900|Layout of the S800}}
+{{:wiki:TriggerGUI.png?900|Trigger schematics of the S800}}
@@ Line 34: / Line 34: @@
 Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward.
-The time stamp module is implemented in a VME XLM72 (SpartanXL) FPGA. The schematics of the firmware is available.  The Verilog code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME bus is also available.
+The time stamp module is implemented in a VME XLM72 (SpartanXL) FPGA. The schematics of the firmware is available here
+[{{:wiki:Stamp64.pdf}}|here]]
+.  The Verilog code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME bus is also available.
 The inputs are the following:

S800 Documentation