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electronics [2013/12/07 17:21] pereira |
electronics [2013/12/10 20:12] pereira [Busy circuit] |
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====== Electronics ====== | ====== Electronics ====== | ||
- | * [[Crate | + | * [[Electronics# |
- | * [[Inventory]] | + | * [[Electronics# |
- | * [[Schematics]] | + | * [[Electronics# |
- | * [[Electronic Diagrama]] | + | * [[Electronics# |
- | ===== General description | + | ===== Crate Configuration |
- | The S800 trigger source comes from the fast timing scintillator [[Detectors# | + | A preliminary scheme of the crate configuration (in progress) |
- | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward. | ||
+ | ===== Inventory Modules ===== | ||
+ | In progress. | ||
- | ===== Trigger Box ===== | + | ===== Electronic Diagrams |
- | The main purpose of the trigger is to implement a coincidence between the S800 focal plane and a secondary detector principally located at the target location. The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. One of the main advantages of this module are: | + | * {{: |
+ | * {{: | ||
+ | * {{:wiki: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
- | - The reduction of cabling and number of modules involved in the implementation of the trigger logic. | ||
- | - The possibility to remotely control and inspect trigger signals, even while beam is present in the vault. | ||
- | - The possibility to save and restore the trigger configuration at any time. | ||
+ | ===== Trigger ===== | ||
+ | The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors# | ||
+ | |||
+ | The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. The main motivations for implementing the trigger logic in an FPGA driven module are the following: | ||
+ | |||
+ | - Simplify cabling and setup of the trigger | ||
+ | - Reduce the number of modules used to implement the trigger | ||
+ | - Ability to remotely control and inspect trigger signals | ||
+ | - Ability to save and restore the trigger configuration | ||
+ | - Direct visualization of the trigger logic and configuration | ||
+ | |||
+ | Probably the most appealing feature of this module is the possibility to remotely control the trigger timing and configuration while beam is present in the vault, since most experiments are nowadays locating their electronics close to the detectors. | ||
+ | |||
+ | The S800 trigger from the [[Detectors# | ||
+ | |||
+ | |||
+ | |||
+ | |||
+ | ===== Trigger Schematics ===== | ||
The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | ||
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+ | The two main trigger sources are labeled " | ||
- | The two main trigger sources are labeled " | ||
+ | ==== Trigger Box ==== | ||
In addition to the singles and coincidence triggers, two separate trigger sources labeled " | In addition to the singles and coincidence triggers, two separate trigger sources labeled " | ||
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- | The S800 trigger | + | ==== Gate generation ==== |
+ | All digitizer gates and start signals are derived | ||
- | ===== Time stamping ===== | ||
- | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward. | ||
- | The time stamp module is implemented in a VME XLM72 (SpartanXL) FPGA. The schematics | + | ==== Inspect channels ==== |
+ | A set of four inspect channels are patched out to the Data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit. | ||
- | [[{{: | + | ==== Busy circuit ==== |
+ | As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The busy circuit following the generation of raw triggers is mainly composed of a latch that is set by the "Raw trigger" | ||
+ | ==== Time stamping ==== | ||
+ | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward. | ||
- | . The Verilog code of the REGISTERS | + | The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the GUI. The clock is inhibited by a " |
- | The inputs are the following: | + | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available [{{: |
- | * E1: time stamp clock input | + | E1: time stamp clock input |
- | | + | |
- | | + | E2: latch input |
+ | |||
+ | E3: clear input | ||
The clear can be done via software as well, and is usually done that way. | The clear can be done via software as well, and is usually done that way. | ||
- | The trigger module FPGA configuration contains a 64 bit counter which is latched by the "Live trigger" | + | Below is the Verilog code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME bus: |
- | The clock signal is released when the " | ||
- | |||
- | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. | ||
- | ===== Busy circuit ===== | ||
- | As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The global busy signal is formed by a logical OR of all busy signals. To eliminate delays caused by the cables routing the individual signals, the S800 trigger uses local latches that are set by the trigger signal and reset by the individual end-of-event signals. The length of the global busy is then determined by the slowest readout sequence. | ||
- | The busy circuit following the generation of raw triggers is mainly composed of a latch that is set by the "Raw trigger" | ||
- | ===== Gate generation ===== | ||
- | All digitizer gates and start signals are derived from the live trigger signal, with the exception of the QDC gate which is directly generated from the S800 source signal. The reason is to avoid long analog delays on the scintillator signals. A fast clear circuit is provided to clear the QDC if no valid trigger was generated. | ||
- | ===== Inspect channels ===== | ||
- | A set of four inspect channels are patched out to the Data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit. | ||
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