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--- electronics [2013/12/10 15:37]
pereira
+++ electronics [2013/12/10 20:41]
pereira
@@ Line 26: / Line 26: @@
 ===== Trigger =====
 The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors#Plastic scintillators|E1]] and a secondary detector principally located at the target location. This coincidence is often a mandatory requirement when the trigger rate of the S800 alone (S800 singles) is too high for the data acquisition and the resulting dead time is prohibitive.
+This section is divided in the following subsections:
+  * Schematics
+  *   * Trigger Box
+  *   * Busy Scheme
+  *   * Time stamping Scheme
+  *   * Gate Generation
+  *   * Inspect Channels
+  *   *
 The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. The main motivations for implementing the trigger logic in an FPGA driven module are the following:
@@ Line 37: / Line 49: @@
 Probably the most appealing feature of this module is the possibility to remotely control the trigger timing and configuration while beam is present in the vault, since most experiments are nowadays locating their electronics close to the detectors.
+The S800 trigger from the [[Detectors#Plastic scintillators|E1 scintillator]] provides also the reference time for the [[Detectors#Cathode Readout Drift Chambers (CRDC)|CRDCs]] as well as time-of-flight measurements. Note that because the FPGA uses a 40 MHz internal clock, the time reference of the signals in the trigger circuit are set the phase of that clock, and therefore jitter by 25 ns with respect to the source signals. This jitter is measured with a TDC and can be subtracted to the time measurements to recover the timing relative to the source signals.
+The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below.
+{{:wiki:TriggerGUI.png?900|Trigger schematics of the S800}}
-===== General description =====
-The S800 trigger source comes from the fast timing scintillator [[Detectors#Plastic scintillators|E1]] located in the focal plane. This trigger can be combined with triggers from other detectors or arrays in order to form coincidences. This is often a mandatory requirement when the trigger rate of the S800 alone (S800 singles) is too high for the data acquisition and the resulting dead time is prohibitive.
+The two main trigger sources are labeled "S800" and "Secondary" in the GUI (the leftmost side of the layout). Each source is routed to a gate and delay generator before forming a coincidence in the following AND gate. The AND signal is then widened before being ANDed with the delayed S800 source signal. The purpose of the second AND gate is to reset the timing of the coincidence to the S800 timing. This is necessary in case the secondary detector has a slow timing and large jitter (Germanium detectors for instance). Single triggers from each trigger source are also available in a second branch, after going through a delay generator followed by a downscaler (used to take a reduced number of events from the trigger sources). Note that each gate and delay generator can be bypassed.
+==== Trigger Box ====
+In addition to the singles and coincidence triggers, two separate trigger sources labeled "External 1" and "External 2" can be used. The various sources can be selected from the trigger box to define the raw trigger, which is then sent to a third AND gate for computer busy rejection. The busy latch (on the middle) is set by the raw trigger after a 50 ns delay, and prevents subsequent events to be accepted. It is reset by the computer once the current event has been processed. The live trigger signal feeds several gate generators which provide appropriate gates for the ADCs, QDCs, TDCs and an eventual coincidence register. Note that the trigger box contains its own coincidence register for which the input signals are delayed by 50 ns, and the gate width is set by the coincidence gate generator. The request event signal is latched before being sent to the computer.
+Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" output of the trigger box may generate two pulses for a single event. A scaler connected to the "Raw trigger" output will therefore not reflect the true number of events. For this reason scalers are also connected to individual inputs of the trigger box (for more details, check section  [[Electronics#Scalers]]    ). A trigger register word (bit pattern) is written at each occurrence of a live trigger signal. This word is the first being read out from the trigger module, prior to the time stamp ([[check trigger packet tag 0x2367 in the DAQ section for more information]]).
+More details about the trigger box module and its FPGA schematics can be found [[here]].
-===== Trigger Box =====
-The main purpose of the trigger is to implement a coincidence between the S800 focal plane and a secondary detector principally located at the target location. The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. One of the main advantages of this module are:
-  -  The reduction of cabling and number of modules involved in the implementation of the trigger logic.
-  -  The possibility to remotely control and inspect trigger signals, even while beam is present in the vault.
-  -  The possibility to save and restore the trigger configuration at any time.
-The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below.
-{{:wiki:TriggerGUI.png?900|Trigger schematics of the S800}}
+==== Gate generation ====
+All digitizer gates and start signals are derived from the live trigger signal, with the exception of the QDC gate which is directly generated from the S800 source signal. The reason is to avoid long analog delays on the scintillator signals. A fast clear circuit is provided to clear the QDC if no valid trigger was generated.
-The two main trigger sources are labeled "S800" and "Secondary" in the GUI. Each source is routed to a gate and delay generator before forming a coincidence in the following AND gate. The AND signal is then widened before being ANDed with the delayed S800 source signal. The purpose of the second AND gate is to reset the timing of the coincidence to the S800 timing. This is necessary in case the secondary detector has a slow timing and large jitter (Germanium detectors for instance). Single triggers from each trigger source are also available in a second branch, after going through a delay generator followed by a downscaler (used to take a reduced number of events from the trigger sources). Note that each gate and delay generator can be bypassed.
+==== Inspect channels ====
+A set of four inspect channels are patched out to the Data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit.
-In addition to the singles and coincidence triggers, two separate trigger sources labeled "External 1" and "External 2" can be used. The various sources can be selected from the trigger box to define the raw trigger, which is then sent to a third AND gate for computer busy rejection. The busy latch (on the middle) is set by the raw trigger after a 50 ns delay, and prevents subsequent events to be accepted. It is reset by the computer once the current event has been processed. The live trigger signal feeds several gate generators which provide appropriate gates for the ADCs, QDCs, TDCs and an eventual coincidence register. Note that the trigger box contains its own coincidence register for which the input signals are delayed by 50 ns, and the gate width is set by the coincidence gate generator. The request event signal is latched before being sent to the computer.
-Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" output of the trigger box may generate two pulses for a single event. A scaler connected to the "Raw trigger" output will therefore not reflect the true number of events. For this reason scalers are also connected to individual inputs of the trigger box. A trigger register word (bit pattern) is written at each occurrence of a live trigger signal. This word is the first being read out from the trigger module, prior to the time stamp.
+==== Busy circuit ====
+As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The busy circuit following the generation of raw triggers is mainly composed of a latch that is set by the "Raw trigger" signal, and cleared by the falling edge of the OR of the individual busy signals (Busy inputs) coming from individual crate controllers or other data acquisition systems. This way the "Live trigger" signal stays true as long as the longest busy signal. The "Live trigger" signal is therefore a "global busy" signal as well. In addition, the same busy signals of individual crate controllers or other data acquisition system are used to veto the "Raw trigger" signal and prevent the generation of a live trigger. This takes care of situations where separate triggers are generated for some of the crate controllers or other data acquisition systems (such as scaler readout sequences), during which no event readout sequence should be started.
-The S800 trigger from the [[Detectors#Plastic scintillators|E1 scintillator]] provides the reference time for the [[Detectors#Cathode Readout Drift Chambers (CRDC)|CRDCs]] as well as time-of-flight measurements. Note that because the FPGA uses a 40 MHz internal clock, the time reference of the signals in the trigger circuit are set the phase of that clock, and therefore jitter by 25 ns with respect to the source signals. This jitter is measured with a TDC and can be subtracted to the time measurements to recover the timing relative to the source signals.
-===== Time stamping =====
+==== Time stamping ====
 Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward.
-The time stamp module is implemented in a VME XLM72 (SpartanXL) FPGA. The schematics of the firmware is available here
+The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the GUI. The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section on [[begin sequence]]). The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized.
+The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available [{{:wiki:Stamp64.pdf}}|here]]. The inputs are the following:
-[[{{:wiki:Stamp64.pdf}}|here]]
+E1: time stamp clock input
+E2: latch input
+E3: clear input
-.  The Verilog code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME bus is also available.
-The inputs are the following:
-  * E1: time stamp clock input
-  * E2: latch input
-  * E3: clear input
 The clear can be done via software as well, and is usually done that way.
-The trigger module FPGA configuration contains a 64 bit counter which is latched by the "Live trigger" signal, and used to time stamp the events. The clock used by default is an internal 10 MHz clock derived from the 40 MHz FPGA clock, although any external clock can also be used, after selecting the appropriate check box in the GUI. The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset, typically during the begin sequences of the controllers or data acquisitions. In addition
+Below is the Verilog code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME bus:
-The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme ensures that all time stamp counters are synchronized.
-The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800.
-===== Busy circuit =====
-As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The global busy signal is formed by a logical OR of all busy signals. To eliminate delays caused by the cables routing the individual signals, the S800 trigger uses local latches that are set by the trigger signal and reset by the individual end-of-event signals. The length of the global busy is then determined by the slowest readout sequence.
-The busy circuit following the generation of raw triggers is mainly composed of a latch that is set by the "Raw trigger" signal, and cleared by the falling edge of the OR of the individual busy signals (Busy inputs) coming from individual crate controllers or other data acquisition systems. This way the "Live trigger" signal stays true as long as the longest busy signal. The "Live trigger" signal is therefore a "global busy" signal as well. In addition, the same busy signals of individual crate controllers or other data acquisition system are used to veto the "Raw trigger" signal and prevent the generation of a live trigger. This takes care of situations where separate triggers are generated for some of the crate controllers or other data acquisition systems (such as scaler readout sequences), during which no event readout sequence should be started.
-===== Gate generation =====
-All digitizer gates and start signals are derived from the live trigger signal, with the exception of the QDC gate which is directly generated from the S800 source signal. The reason is to avoid long analog delays on the scintillator signals. A fast clear circuit is provided to clear the QDC if no valid trigger was generated.
-===== Inspect channels =====
-A set of four inspect channels are patched out to the Data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit.

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