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electronics [2013/12/10 20:17] pereira [Trigger Box] |
electronics [2013/12/10 20:47] pereira |
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===== Trigger ===== | ===== Trigger ===== | ||
The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors# | The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors# | ||
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+ | This section is divided in the following subsections: | ||
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+ | - Ordered List ItemSchematics | ||
+ | - Trigger Box | ||
+ | - Busy Scheme | ||
+ | * Time stamping Scheme | ||
+ | * Gate Generation | ||
+ | * Inspect Channel | ||
+ | * Trigger Module | ||
+ | * CAMAC Commands | ||
+ | * Inputs and Outputs | ||
+ | * FPGA firmware | ||
+ | * Time Stamping | ||
+ | Configuration for S800 in tandem with other detectors | ||
+ | 4 Begin sequence | ||
+ | 5 Scalers and dead time | ||
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The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. The main motivations for implementing the trigger logic in an FPGA driven module are the following: | The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. The main motivations for implementing the trigger logic in an FPGA driven module are the following: | ||
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- | ===== Trigger Schematics ===== | ||
The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | ||
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Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" | Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" | ||
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+ | More details about the trigger box module and its FPGA schematics can be found [[here]]. | ||
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