S800 Documentation

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electronics [2013/12/10 20:23]
pereira 		electronics [2013/12/10 20:41]
pereira
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 ===== Trigger ===== ===== Trigger =====
 The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors#Plastic scintillators|E1]] and a secondary detector principally located at the target location. This coincidence is often a mandatory requirement when the trigger rate of the S800 alone (S800 singles) is too high for the data acquisition and the resulting dead time is prohibitive.  The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors#Plastic scintillators|E1]] and a secondary detector principally located at the target location. This coincidence is often a mandatory requirement when the trigger rate of the S800 alone (S800 singles) is too high for the data acquisition and the resulting dead time is prohibitive. 
 +
 +This section is divided in the following subsections:
 +
 +  * Schematics
 +  *   * Trigger Box
 +  *   * Busy Scheme
 +  *   * Time stamping Scheme
 +  *   * Gate Generation
 +  *   * Inspect Channels
 +  *   * 
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 +
  
 The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. The main motivations for implementing the trigger logic in an FPGA driven module are the following:  The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. The main motivations for implementing the trigger logic in an FPGA driven module are the following: 
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 Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" output of the trigger box may generate two pulses for a single event. A scaler connected to the "Raw trigger" output will therefore not reflect the true number of events. For this reason scalers are also connected to individual inputs of the trigger box (for more details, check section  [[Electronics#Scalers]]    ). A trigger register word (bit pattern) is written at each occurrence of a live trigger signal. This word is the first being read out from the trigger module, prior to the time stamp ([[check trigger packet tag 0x2367 in the DAQ section for more information]]).  Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" output of the trigger box may generate two pulses for a single event. A scaler connected to the "Raw trigger" output will therefore not reflect the true number of events. For this reason scalers are also connected to individual inputs of the trigger box (for more details, check section  [[Electronics#Scalers]]    ). A trigger register word (bit pattern) is written at each occurrence of a live trigger signal. This word is the first being read out from the trigger module, prior to the time stamp ([[check trigger packet tag 0x2367 in the DAQ section for more information]]). 
  
-As explained above, the trigger logic is implemented in a LeCroy 2367 ULM by means of its XC4000E Xilinx FPGA. The schematics of the firmware can be found [[here]].+More details about the trigger box module and its FPGA schematics can be found [[here]]. 
 + 
  
  
electronics.txt · Last modified: 2023/10/16 08:25 by noji

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