This shows you the differences between two versions of the page.
Both sides previous revision Previous revision Next revision | Previous revision Next revision Both sides next revision | ||
electronics [2013/12/10 20:34] pereira [Trigger Box] |
electronics [2013/12/10 20:46] pereira |
||
---|---|---|---|
Line 26: | Line 26: | ||
===== Trigger ===== | ===== Trigger ===== | ||
The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors# | The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors# | ||
+ | |||
+ | This section is divided in the following subsections: | ||
+ | |||
+ | - Ordered List ItemSchematics | ||
+ | - - Ordered List ItemTrigger Box | ||
+ | * Busy Scheme | ||
+ | * Time stamping Scheme | ||
+ | * Gate Generation | ||
+ | * Inspect Channel | ||
+ | * Trigger Module | ||
+ | * CAMAC Commands | ||
+ | * Inputs and Outputs | ||
+ | * FPGA firmware | ||
+ | * Time Stamping | ||
+ | Configuration for S800 in tandem with other detectors | ||
+ | 4 Begin sequence | ||
+ | 5 Scalers and dead time | ||
+ | |||
+ | |||
+ | |||
The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. The main motivations for implementing the trigger logic in an FPGA driven module are the following: | The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. The main motivations for implementing the trigger logic in an FPGA driven module are the following: |