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trigger [2013/12/10 21:14] pereira created |
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+ | ====== Trigger ====== | ||
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====== Trigger ====== | ====== Trigger ====== | ||
The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors# | The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors# | ||
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- | ==== Busy circuit | + | ==== Busy Circuit |
As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The busy circuit following the generation of raw triggers is mainly composed of a latch that is set by the "Raw trigger" | As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The busy circuit following the generation of raw triggers is mainly composed of a latch that is set by the "Raw trigger" | ||
==== Time Stamping Scheme ==== | ==== Time Stamping Scheme ==== | ||
- | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward. | + | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward. |
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- | ===== Time Stamping ===== | + | |
- | The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the GUI. The clock is inhibited by a " | + | |
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- | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available [{{: | + | |
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- | E1: time stamp clock input | + | |
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- | E2: latch input | + | |
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- | E3: clear input | + | |
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- | The clear can be done via software as well, and is usually done that way. | + | |
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- | Below is the Verilog code of the REGISTERS module of the FPGA configuration, | + | |
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- | ===== Configuration for S800 in tandem with other detectors ===== | + | |
- | In its standard configuration, | + | |
- | To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following: | + | |
- | • Raw trigger from external detector to Secondary source | + | |
- | • Live trigger from S800 trigger to external data acquisition (trigger input) | + | |
- | • Time stamp clock from S800 trigger to external data acquisition (time stamp input) | + | |
- | • End-of-event from external data acquisition to S800 trigger | + | |
- | • Busy from external data acquisition to S800 trigger | + | |
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- | ===== Begin sequence ===== | + | |
- | The internal " | + | |
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- | The data acquisition begin sequence of the trigger module is the following: | + | |
- | reset time stamp counter to 0 | + | |
- | reset trigger register to 0 | + | |
- | after all modules in all crates have been initialized, | + | |
- | after a preset delay of 200 to 300 microseconds, | + | |
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- | The last step of the begin sequence allows enough time for the CCUSB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the " | + | |
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- | ===== Scalers and dead time ===== | + | |
- | The " | + | |
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- | In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger. | + | |
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+ | ===== Time Stamping ===== | ||
+ | The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger# | ||
+ | |||
+ | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available [{{: | ||
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+ | E1: time stamp clock input | ||
+ | |||
+ | E2: latch input | ||
+ | |||
+ | E3: clear input | ||
+ | |||
+ | The clear can be done via software as well, and is usually done that way. | ||
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+ | Below is the Verilog code of the REGISTERS module of the FPGA configuration, | ||
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+ | NWRX, | ||
+ | ACKX, | ||
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+ | ) ; | ||
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+ | input NSELX ; | ||
+ | input NWRX ; | ||
+ | input ACKX ; | ||
+ | input [20:2] ADRIN ; | ||
+ | input [31:0] DATAIN ; | ||
+ | input [63:0] ScalerA ; | ||
+ | | ||
+ | | ||
+ | | ||
+ | |||
+ | // add your declarations here | ||
+ | reg Clear; | ||
+ | reg [31:0] DATAOUT; | ||
+ | reg DataDrive; | ||
+ | |||
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+ | // Write from VME to FPGA | ||
+ | // Addresses and Data are driven by VME | ||
+ | if (!NSELX & !NWRX & !ACKX) begin | ||
+ | | ||
+ | | ||
+ | case (ADRIN) | ||
+ | 0: Clear = DATAIN[0]; | ||
+ | | ||
+ | end | ||
+ | |||
+ | // Read from FPGA to VME | ||
+ | // Addresses driven by VME - Data driven by FPGA | ||
+ | else if (!NSELX & NWRX & !ACKX) begin | ||
+ | | ||
+ | case (ADRIN) | ||
+ | 00: DATAOUT = 32' | ||
+ | 01: DATAOUT = ScalerA[31: | ||
+ | 02: DATAOUT = ScalerA[63: | ||
+ | | ||
+ | | ||
+ | end | ||
+ | |||
+ | // VME not accessing FPGA | ||
+ | else if (NSELX & NWRX & ACKX) begin | ||
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+ | end | ||
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+ | end | ||
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+ | ===== Configuration for S800 in tandem with other detectors ===== | ||
+ | In its standard configuration, | ||
+ | To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following: | ||
+ | |||
+ | - Raw trigger from external detector to Secondary source | ||
+ | - Live trigger from S800 trigger to external data acquisition (trigger input) | ||
+ | - Time stamp clock from S800 trigger to external data acquisition (time stamp input) | ||
+ | - End-of-event from external data acquisition to S800 trigger | ||
+ | - Busy from external data acquisition to S800 trigger | ||
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+ | ===== Begin sequence ===== | ||
+ | The internal " | ||
+ | |||
+ | The data acquisition begin sequence of the trigger module is the following: | ||
+ | reset time stamp counter to 0 | ||
+ | reset trigger register to 0 | ||
+ | after all modules in all crates have been initialized, | ||
+ | after a preset delay of 200 to 300 microseconds, | ||
+ | |||
+ | The last step of the begin sequence allows enough time for the CCUSB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the " | ||
+ | |||
+ | ===== Scalers and dead time ===== | ||
+ | The " | ||
+ | |||
+ | In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger. | ||
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