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trigger [2013/12/10 21:14] pereira created |
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- | ====== Trigger ====== | ||
The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors# | The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors# | ||
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- | ===== Trigger Schematic ===== | + | ====== Trigger Schematic ====== |
+ | |||
The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | ||
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- | ==== Trigger Box ==== | + | ===== Trigger Box ===== |
In addition to the singles and coincidence triggers, two separate trigger sources labeled " | In addition to the singles and coincidence triggers, two separate trigger sources labeled " | ||
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- | ==== Gate generation ==== | + | ===== Gate generation |
All digitizer gates and start signals are derived from the live trigger signal, with the exception of the QDC gate which is directly generated from the S800 source signal. The reason is to avoid long analog delays on the scintillator signals. A fast clear circuit is provided to clear the QDC if no valid trigger was generated. | All digitizer gates and start signals are derived from the live trigger signal, with the exception of the QDC gate which is directly generated from the S800 source signal. The reason is to avoid long analog delays on the scintillator signals. A fast clear circuit is provided to clear the QDC if no valid trigger was generated. | ||
- | ==== Inspect channels ==== | + | ===== Inspect channels |
A set of four inspect channels are patched out to the Data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit. | A set of four inspect channels are patched out to the Data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit. | ||
- | ==== Busy circuit | + | ===== Busy Circuit ===== |
As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The busy circuit following the generation of raw triggers is mainly composed of a latch that is set by the "Raw trigger" | As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The busy circuit following the generation of raw triggers is mainly composed of a latch that is set by the "Raw trigger" | ||
- | ==== Time Stamping Scheme ==== | + | ===== Time Stamping Scheme |
- | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward. | + | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward. More details about the time stamping can be found [[Trigger# |
+ | ====== Trigger module ====== | ||
+ | The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/ | ||
+ | ===== CAMAC commands ===== | ||
+ | The following table lists the CAMAC codes recognized by the trigger module and their signification. | ||
- | ===== Time Stamping ===== | + | F A Direction |
- | The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the GUI. The clock is inhibited by a " | + | 0 0 Read 16 0 Write S800 Gate & Delay (delay) |
+ | 0 1 Read 16 1 Write S800 Gate & Delay (width) | ||
+ | 0 2 Read 16 2 Write Secondary Gate & Delay (delay) | ||
+ | 0 3 Read 16 3 Write Secondary Gate & Delay (width) | ||
+ | 0 4 Read 16 4 Write S800 Delay (delay) | ||
+ | 0 5 Read 16 5 Write Coincidence Gate (width) | ||
+ | 0 6 Read 16 6 Write Secondary Delay (delay) | ||
+ | 0 7 Read 16 7 Write Bypasses (bit pattern) | ||
+ | 0 8 Read 16 8 Write S800 Downscaler (factor) | ||
+ | 0 9 Read 16 9 Write Secondary Downscaler (factor) | ||
+ | 0 10 Read 16 10 Write Trigger Box (bit pattern) | ||
+ | 0 11 Read 16 11 Write Go signal (bit) | ||
+ | 0 12 Read 16 12 Write External Time Stamp Clock (bit 0) | ||
+ | and External Time Stamp Latch (bit 1) | ||
+ | |||
+ | 0 14 Read | ||
+ | 0 15 Read | ||
+ | 1 0 Read 17 0 Write Inspect Channel 1 (wire) | ||
+ | 1 1 Read 17 1 Write Inspect Channel 2 (wire) | ||
+ | 1 2 Read 17 2 Write Inspect Channel 3 (wire) | ||
+ | 1 3 Read 17 3 Write Inspect Channel 4 (wire) | ||
+ | 2 0 Read 18 0 Write ADC Gate (width) | ||
+ | 2 1 Read 18 1 Write QDC Gate (width) | ||
+ | 2 2 Read 18 2 Write TDC Gate (width) | ||
+ | 2 3 Read 18 3 Write Coincidence Register Gate (width) | ||
+ | 3 0 Read | ||
+ | 3 1 Read Time Stamp (bits 0-15) | ||
+ | 3 2 Read Time Stamp (bits 16-31) | ||
+ | 3 3 Read Time Stamp (bits 32-47) | ||
+ | 3 4 Read Time Stamp (bits 48-63) | ||
+ | |||
+ | |||
+ | ===== Inputs and outputs ===== | ||
+ | The following table lists the inputs and outputs to/from the trigger module and their assignment. | ||
+ | |||
+ | Pin Assignment | ||
+ | A1 (in) S800 source | ||
+ | A2 (in) Secondary source | ||
+ | A3 (in) External 1 source | ||
+ | A4 (in) External 2 source | ||
+ | A5 (in) Clear busy B5 (out) TDC start C5 (in) Busy 5 D5 (out) S800 trigger | ||
+ | A6 (in) Clear module | ||
+ | A7 (in) Gretina sync B7 (out) C7 (in) Busy 7 D7 (out) External 1 trigger | ||
+ | A8 (in) Time stamp clock B8 (out) Live trigger | ||
+ | B9 (out) Inspect 1 C9 (out) Time stamp clock D9 (out) Secondary trigger | ||
+ | B10 (out) Inspect 2 C10 (out) Time stamp latch D10 (out) Raw trigger | ||
+ | B11 (out) Inspect 3 C11 (out) D11 (out) Live trigger | ||
+ | B12 (out) Inspect 4 C12 (out) D12 (out) Raw pulser | ||
+ | B13 (out) Fast clear C13 (out) D13 (out) Live pulser | ||
+ | B14 (out) C14 (out) D14 (out) Fast clear | ||
+ | B15 (out) Go C15 (out) D15 (out) 10 Hz | ||
+ | B16 (out) Time stamp clock C16 (out) D16 (out) 1 Hz | ||
+ | |||
+ | ===== FPGA firmware ===== | ||
+ | The firmware of the trigger module is shown in the following files. The PDF file contains the schematic sheets, used for most of the design. The Verilog file contains the block dealing with CAMAC communications. | ||
+ | |||
+ | File containing the schematics: File: | ||
+ | |||
+ | Below is the Verilog code used in the configuration for the INTERNAL module: | ||
+ | ................ | ||
+ | .................... | ||
+ | |||
+ | |||
+ | |||
+ | |||
+ | ====== Time Stamping | ||
+ | The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger# | ||
The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available [{{: | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available [{{: | ||
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Below is the Verilog code of the REGISTERS module of the FPGA configuration, | Below is the Verilog code of the REGISTERS module of the FPGA configuration, | ||
+ | ........ | ||
+ | ........ | ||
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- | ===== Configuration for S800 in tandem with other detectors ===== | + | |
+ | |||
+ | ====== Configuration for S800 in tandem with other detectors | ||
In its standard configuration, | In its standard configuration, | ||
To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following: | To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following: | ||
- | • Raw trigger from external detector to Secondary source | ||
- | • Live trigger from S800 trigger to external data acquisition (trigger input) | ||
- | • Time stamp clock from S800 trigger to external data acquisition (time stamp input) | ||
- | • End-of-event from external data acquisition to S800 trigger | ||
- | • Busy from external data acquisition to S800 trigger | ||
+ | - Raw trigger from external detector to Secondary source | ||
+ | - Live trigger from S800 trigger to external data acquisition (trigger input) | ||
+ | - Time stamp clock from S800 trigger to external data acquisition (time stamp input) | ||
+ | - End-of-event from external data acquisition to S800 trigger | ||
+ | - Busy from external data acquisition to S800 trigger | ||
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- | + | ====== Begin sequence | |
- | ===== Begin sequence ===== | + | |
The internal " | The internal " | ||
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- | ===== Trigger module ===== | ||
- | |||
- | The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/ | ||
- | |||
- | ==== CAMAC commands ==== | ||
- | |||
- | The following table lists the CAMAC codes recognized by the trigger module and their signification. | ||
- | |||
- | F A Direction | ||
- | 0 0 Read 16 0 Write S800 Gate & Delay (delay) | ||
- | 0 1 Read 16 1 Write S800 Gate & Delay (width) | ||
- | 0 2 Read 16 2 Write Secondary Gate & Delay (delay) | ||
- | 0 3 Read 16 3 Write Secondary Gate & Delay (width) | ||
- | 0 4 Read 16 4 Write S800 Delay (delay) | ||
- | 0 5 Read 16 5 Write Coincidence Gate (width) | ||
- | 0 6 Read 16 6 Write Secondary Delay (delay) | ||
- | 0 7 Read 16 7 Write Bypasses (bit pattern) | ||
- | 0 8 Read 16 8 Write S800 Downscaler (factor) | ||
- | 0 9 Read 16 9 Write Secondary Downscaler (factor) | ||
- | 0 10 Read 16 10 Write Trigger Box (bit pattern) | ||
- | 0 11 Read 16 11 Write Go signal (bit) | ||
- | 0 12 Read 16 12 Write External Time Stamp Clock (bit 0) | ||
- | and External Time Stamp Latch (bit 1) | ||
- | |||
- | 0 14 Read | ||
- | 0 15 Read | ||
- | 1 0 Read 17 0 Write Inspect Channel 1 (wire) | ||
- | 1 1 Read 17 1 Write Inspect Channel 2 (wire) | ||
- | 1 2 Read 17 2 Write Inspect Channel 3 (wire) | ||
- | 1 3 Read 17 3 Write Inspect Channel 4 (wire) | ||
- | 2 0 Read 18 0 Write ADC Gate (width) | ||
- | 2 1 Read 18 1 Write QDC Gate (width) | ||
- | 2 2 Read 18 2 Write TDC Gate (width) | ||
- | 2 3 Read 18 3 Write Coincidence Register Gate (width) | ||
- | 3 0 Read | ||
- | 3 1 Read Time Stamp (bits 0-15) | ||
- | 3 2 Read Time Stamp (bits 16-31) | ||
- | 3 3 Read Time Stamp (bits 32-47) | ||
- | 3 4 Read Time Stamp (bits 48-63) | ||
- | |||
- | ==== Inputs and outputs ==== | ||
- | |||
- | The following table lists the inputs and outputs to/from the trigger module and their assignment. | ||
- | |||
- | Pin Assignment | ||
- | A1 (in) S800 source | ||
- | A2 (in) Secondary source | ||
- | A3 (in) External 1 source | ||
- | A4 (in) External 2 source | ||
- | A5 (in) Clear busy B5 (out) TDC start C5 (in) Busy 5 D5 (out) S800 trigger | ||
- | A6 (in) Clear module | ||
- | A7 (in) Gretina sync B7 (out) C7 (in) Busy 7 D7 (out) External 1 trigger | ||
- | A8 (in) Time stamp clock B8 (out) Live trigger | ||
- | B9 (out) Inspect 1 C9 (out) Time stamp clock D9 (out) Secondary trigger | ||
- | B10 (out) Inspect 2 C10 (out) Time stamp latch D10 (out) Raw trigger | ||
- | B11 (out) Inspect 3 C11 (out) D11 (out) Live trigger | ||
- | B12 (out) Inspect 4 C12 (out) D12 (out) Raw pulser | ||
- | B13 (out) Fast clear C13 (out) D13 (out) Live pulser | ||
- | B14 (out) C14 (out) D14 (out) Fast clear | ||
- | B15 (out) Go C15 (out) D15 (out) 10 Hz | ||
- | B16 (out) Time stamp clock C16 (out) D16 (out) 1 Hz | ||
- | |||
- | ==== FPGA firmware ==== | ||
- | The firmware of the trigger module is shown in the following files. The PDF file contains the schematic sheets, used for most of the design. The Verilog file contains the block dealing with CAMAC communications. | ||
- | |||
- | File containing the schematics: File: | ||
- | |||
- | Below is the Verilog code used in the configuration for the INTERNAL module: | ||
- | | ||
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- | ) ; | ||
- | |||
- | input N ; | ||
- | input S1 ; | ||
- | input S2 ; | ||
- | input Clock ; | ||
- | input [4:0] F ; | ||
- | input [3:0] A ; | ||
- | input [23:0] Data_in ; | ||
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- | input [4:0] Register; | ||
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- | | ||
- | input [63:0] TimeStamp; | ||
- | | ||
- | | ||
- | |||
- | // add your declarations here | ||
- | reg X; | ||
- | reg Q; | ||
- | reg DriveRead ; | ||
- | reg ClearModule; | ||
- | reg ClearRegister; | ||
- | reg Go; | ||
- | reg [1:0] Select; | ||
- | reg SyncEnable; | ||
- | reg [23:0] Data_out ; | ||
- | reg [7:0] S800Delay; | ||
- | reg [7:0] S800Width ; | ||
- | reg [7:0] SecondaryDelay; | ||
- | reg [7:0] SecondaryWidth ; | ||
- | reg [7:0] S800TimingDelay; | ||
- | reg [7:0] CoincTimingWidth ; | ||
- | reg [7:0] SecondaryTimingDelay ; | ||
- | reg [4:0] Bypasses ; | ||
- | reg [9:0] S800Factor ; | ||
- | reg [9:0] SecondaryFactor ; | ||
- | reg [4:0] TriggerBox ; | ||
- | reg [7:0] ADCGate ; | ||
- | reg [7:0] QDCGate ; | ||
- | reg [7:0] TDCStart ; | ||
- | reg [7:0] Coincidence ; | ||
- | reg [4:0] Inspect1 ; | ||
- | reg [4:0] Inspect2 ; | ||
- | reg [4:0] Inspect3 ; | ||
- | reg [4:0] Inspect4 ; | ||
- | |||
- | // add your code here | ||
- | | ||
- | if (N) begin | ||
- | case (F) | ||
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- | case (A) | ||
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- | end // F=0 | ||
- | |||
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- | case (A) | ||
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- | end // F=1 | ||
- | |||
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- | case (A) | ||
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- | end // F=2 | ||
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- | case (A) | ||
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- | end // F=3 | ||
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- | end // F=9 | ||
- | |||
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- | if (S1) begin | ||
- | case (A) | ||
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- | end // S1=1 | ||
- | end // F=16 | ||
- | |||
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- | if (S1) begin | ||
- | case (A) | ||
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- | end // S1=1 | ||
- | end // F=17 | ||
- | |||
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- | if (S1) begin | ||
- | case (A) | ||
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- | end // S1=1 | ||
- | end // F=18 | ||
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- | end //N=1 | ||
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- | end // always Clock | ||
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- | if (N) begin | ||
- | |||
- | case (F) | ||
- | |||
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- | X = 1'b1; | ||
- | Q = 1'b1; | ||
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- | end // F=0 | ||
- | |||
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- | X = 1'b1; | ||
- | Q = 1'b1; | ||
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- | end // F=1 | ||
- | |||
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- | X = 1'b1; | ||
- | Q = 1'b1; | ||
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- | end // F=2 | ||
- | |||
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- | X = 1'b1; | ||
- | Q = 1'b1; | ||
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- | end // F=3 | ||
- | |||
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- | X = 1'b1; | ||
- | Q = 1'b1; | ||
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- | end // F=9 | ||
- | |||
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- | X = 1'b1; | ||
- | Q = 1'b1; | ||
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- | end // F=9 | ||
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- | X = 1'b1; | ||
- | Q = 1'b1; | ||
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- | end // F=16 | ||
- | |||
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- | X = 1'b1; | ||
- | Q = 1'b1; | ||
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- | end // F=17 | ||
- | |||
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- | X = 1'b1; | ||
- | Q = 1'b1; | ||
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- | end // F=18 | ||
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- | X = 1'b0; | ||
- | Q = 1'b0; | ||
- | end // default F | ||
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- | end // if (N) | ||
- | |||
- | else begin | ||
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- | X = 1'b0; | ||
- | Q = 1'b0; | ||
- | end // if (!N) | ||
- | end // always N or S1 or A or F | ||
- | |||
- | | ||