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--- trigger [2013/12/10 21:15]
pereira [Configuration for S800 in tandem with other detectors]
+++ trigger [2013/12/10 21:25]
pereira
@@ Line 1: / Line 1: @@
-====== Trigger ======
+====== **Trigger** ======
 The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors#Plastic scintillators|E1]] and a secondary detector principally located at the target location. This coincidence is often a mandatory requirement when the trigger rate of the S800 alone (S800 singles) is too high for the data acquisition and the resulting dead time is prohibitive.
@@ Line 15: / Line 15: @@
-===== Trigger Schematic =====
+===== **Trigger Schematic** =====
 The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below.
@@ Line 39: / Line 39: @@
-==== Busy circuit ====
+==== Busy Circuit ====
 As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The busy circuit following the generation of raw triggers is mainly composed of a latch that is set by the "Raw trigger" signal, and cleared by the falling edge of the OR of the individual busy signals (Busy inputs) coming from individual crate controllers or other data acquisition systems. This way the "Live trigger" signal stays true as long as the longest busy signal. The "Live trigger" signal is therefore a "global busy" signal as well. In addition, the same busy signals of individual crate controllers or other data acquisition system are used to veto the "Raw trigger" signal and prevent the generation of a live trigger. This takes care of situations where separate triggers are generated for some of the crate controllers or other data acquisition systems (such as scaler readout sequences), during which no event readout sequence should be started.
 ==== Time Stamping Scheme ====
-Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward.
+Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward. More details about the time stamping can be found [[Trigger#Time Stamping|here]].
+===== **Trigger module** =====
-===== Time Stamping =====
-The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the GUI. The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section on [[begin sequence]]). The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized.
-The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available [{{:wiki:Stamp64.pdf}}|here]]. The inputs are the following:
-E1: time stamp clock input
-E2: latch input
-E3: clear input
-The clear can be done via software as well, and is usually done that way.
-Below is the Verilog code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME bus:
-===== Configuration for S800 in tandem with other detectors =====
-In its standard configuration, the S800 data acquisition uses one CAMAC crate and one VME crate only. The CC-USB and VM-USB crate controller modules performing the readout are connected to the latches number 1 and 2 of the trigger module, respectively. Each crate controller is configured to output their busy and end-of-event signals on their available NIM outputs, which are then connected to the appropriate inputs on the trigger module.
-To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following:
-- Raw trigger from external detector to Secondary source
-- Live trigger from S800 trigger to external data acquisition (trigger input)
-- Time stamp clock from S800 trigger to external data acquisition (time stamp input)
-- End-of-event from external data acquisition to S800 trigger
-- Busy from external data acquisition to S800 trigger
-===== Begin sequence =====
-The internal "Go" state of the trigger module is controlled via CAMAC commands. When "Go" is false, the trigger and time stamp clock signals are vetoed and therefore absent. This way all time stamp counters can be safely zeroed during the beginning sequence of the data acquisition systems. The last command of the CAMAC beginning sequence sets the "Go" state to true, at which point both trigger and time stamp signals are released. This mechanism ensures that all time stamp counters are synchronized.
-The data acquisition begin sequence of the trigger module is the following:
- reset time stamp counter to 0
- reset trigger register to 0
- after all modules in all crates have been initialized, send CAMAC command to set "Go" state to true
- after a preset delay of 200 to 300 microseconds, the "Go" level is set to true
-The last step of the begin sequence allows enough time for the CCUSB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the "Go" state of the module back to false.
-===== Scalers and dead time =====
-The "D" connector of the trigger module is directly connected to 16 inputs of a scaler module (see mapping in the inputs and outputs section below). Scalers are connected to each of the trigger source inputs, as well as trigger box inputs. These scalers can be used to recover the number of trigger signals occurring on each of the source and trigger box inputs, in addition to the information coded for each event in the trigger register.
-In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger.
-===== Trigger module =====
 The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/outputs (such as the VME XLM72 module for instance). This section describes the functionality of the S800 trigger module and the commands used to control its parameters.
@@ Line 478: / Line 402: @@
  endmodule
+===== Time Stamping =====
+The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger#Trigger Schematic|GUI]]). The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section on [[begin sequence]]). The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized.
+The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available [{{:wiki:Stamp64.pdf}}|here]]. The inputs are the following:
+E1: time stamp clock input
+E2: latch input
+E3: clear input
+The clear can be done via software as well, and is usually done that way.
+Below is the Verilog code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME bus:
+ module Registers (
+ NSELX,
+ NWRX,
+ ACKX,
+ ADRIN,
+ DATAIN,
+ DATAOUT,
+ DataDrive,
+ Clear,
+ ScalerA
+ ) ;
+ input NSELX ;
+ input NWRX ;
+ input ACKX ;
+ input [20:2] ADRIN ;
+ input [31:0] DATAIN ;
+ input [63:0] ScalerA ;
+ output [31:0] DATAOUT ;
+ output Clear ;
+ output DataDrive;
+ // add your declarations here
+ reg Clear;
+ reg [31:0] DATAOUT;
+ reg DataDrive;
+ always @(NSELX or NWRX or ACKX or DATAIN or ADRIN) begin
+   DataDrive = 0;
+   DATAOUT = 32'd0;
+ // Write from VME to FPGA
+ // Addresses and Data are driven by VME
+   if (!NSELX & !NWRX & !ACKX) begin
+   DataDrive = 0;
+   DATAOUT = 32'd0;
+   case (ADRIN)
+: Clear = DATAIN[0];
+   endcase //ADRIN
+   end
+ // Read from FPGA to VME
+ // Addresses driven by VME - Data driven by FPGA
+   else if (!NSELX & NWRX & !ACKX) begin
+   DataDrive = 1;
+   case (ADRIN)
+: DATAOUT = 32'hDABA0002;
+: DATAOUT = ScalerA[31:0];
+: DATAOUT = ScalerA[63:32];
+     default: DATAOUT = 32'd0;
+   endcase
+   end
+ // VME not accessing FPGA
+   else if (NSELX & NWRX & ACKX) begin
+   DataDrive = 1;
+   DATAOUT = 32'd0;
+   end
+ end
+ endmodule
+===== Configuration for S800 in tandem with other detectors =====
+In its standard configuration, the S800 data acquisition uses one CAMAC crate and one VME crate only. The CC-USB and VM-USB crate controller modules performing the readout are connected to the latches number 1 and 2 of the trigger module, respectively. Each crate controller is configured to output their busy and end-of-event signals on their available NIM outputs, which are then connected to the appropriate inputs on the trigger module.
+To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following:
+  - Raw trigger from external detector to Secondary source
+  - Live trigger from S800 trigger to external data acquisition (trigger input)
+  - Time stamp clock from S800 trigger to external data acquisition (time stamp input)
+  - End-of-event from external data acquisition to S800 trigger
+  - Busy from external data acquisition to S800 trigger
+===== Begin sequence =====
+The internal "Go" state of the trigger module is controlled via CAMAC commands. When "Go" is false, the trigger and time stamp clock signals are vetoed and therefore absent. This way all time stamp counters can be safely zeroed during the beginning sequence of the data acquisition systems. The last command of the CAMAC beginning sequence sets the "Go" state to true, at which point both trigger and time stamp signals are released. This mechanism ensures that all time stamp counters are synchronized.
+The data acquisition begin sequence of the trigger module is the following:
+ reset time stamp counter to 0
+ reset trigger register to 0
+ after all modules in all crates have been initialized, send CAMAC command to set "Go" state to true
+ after a preset delay of 200 to 300 microseconds, the "Go" level is set to true
+The last step of the begin sequence allows enough time for the CCUSB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the "Go" state of the module back to false.
+===== Scalers and dead time =====
+The "D" connector of the trigger module is directly connected to 16 inputs of a scaler module (see mapping in the inputs and outputs section below). Scalers are connected to each of the trigger source inputs, as well as trigger box inputs. These scalers can be used to recover the number of trigger signals occurring on each of the source and trigger box inputs, in addition to the information coded for each event in the trigger register.
+In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger.

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