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trigger [2013/12/10 21:21] pereira |
trigger [2013/12/10 21:34] pereira |
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- | ====== Trigger ====== | ||
The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors# | The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors# | ||
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- | ===== Trigger Schematic ===== | + | ====== Trigger Schematic ====== |
+ | |||
The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | ||
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==== Busy Circuit ==== | ==== Busy Circuit ==== | ||
As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The busy circuit following the generation of raw triggers is mainly composed of a latch that is set by the "Raw trigger" | As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The busy circuit following the generation of raw triggers is mainly composed of a latch that is set by the "Raw trigger" | ||
- | |||
==== Time Stamping Scheme ==== | ==== Time Stamping Scheme ==== | ||
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- | ===== Trigger module ===== | + | ====== Trigger module ====== |
The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/ | The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/ | ||
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3 4 Read Time Stamp (bits 48-63) | 3 4 Read Time Stamp (bits 48-63) | ||
- | ==== Inputs and outputs ==== | ||
+ | ==== Inputs and outputs ==== | ||
The following table lists the inputs and outputs to/from the trigger module and their assignment. | The following table lists the inputs and outputs to/from the trigger module and their assignment. | ||
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Below is the Verilog code used in the configuration for the INTERNAL module: | Below is the Verilog code used in the configuration for the INTERNAL module: | ||
- | | + | ................ |
- | DriveRead, Q, X, Data_out, | + | .................... |
- | | + | |
- | | + | |
- | | + | |
- | | + | |
- | | + | |
- | | + | |
- | | + | |
- | | + | |
- | | + | |
- | ) ; | + | |
- | + | ||
- | input N ; | + | |
- | input S1 ; | + | |
- | input S2 ; | + | |
- | input Clock ; | + | |
- | input [4:0] F ; | + | |
- | input [3:0] A ; | + | |
- | input [23:0] Data_in ; | + | |
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- | | + | |
- | input [4:0] Register; | + | |
- | | + | |
- | | + | |
- | | + | |
- | input [63:0] TimeStamp; | + | |
- | | + | |
- | | + | |
- | + | ||
- | // add your declarations here | + | |
- | reg X; | + | |
- | reg Q; | + | |
- | reg DriveRead ; | + | |
- | reg ClearModule; | + | |
- | reg ClearRegister; | + | |
- | reg Go; | + | |
- | reg [1:0] Select; | + | |
- | reg SyncEnable; | + | |
- | reg [23:0] Data_out ; | + | |
- | reg [7:0] S800Delay; | + | |
- | reg [7:0] S800Width ; | + | |
- | reg [7:0] SecondaryDelay; | + | |
- | reg [7:0] SecondaryWidth ; | + | |
- | reg [7:0] S800TimingDelay; | + | |
- | reg [7:0] CoincTimingWidth ; | + | |
- | reg [7:0] SecondaryTimingDelay ; | + | |
- | reg [4:0] Bypasses ; | + | |
- | reg [9:0] S800Factor ; | + | |
- | reg [9:0] SecondaryFactor ; | + | |
- | reg [4:0] TriggerBox ; | + | |
- | reg [7:0] ADCGate ; | + | |
- | reg [7:0] QDCGate ; | + | |
- | reg [7:0] TDCStart ; | + | |
- | reg [7:0] Coincidence ; | + | |
- | reg [4:0] Inspect1 ; | + | |
- | reg [4:0] Inspect2 ; | + | |
- | reg [4:0] Inspect3 ; | + | |
- | reg [4:0] Inspect4 ; | + | |
- | + | ||
- | // add your code here | + | |
- | | + | |
- | if (N) begin | + | |
- | case (F) | + | |
- | | + | |
- | case (A) | + | |
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- | end // F=0 | + | |
- | + | ||
- | | + | |
- | case (A) | + | |
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- | end // F=1 | + | |
- | + | ||
- | | + | |
- | case (A) | + | |
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- | | + | |
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- | | + | |
- | end // F=2 | + | |
- | + | ||
- | | + | |
- | case (A) | + | |
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- | | + | |
- | | + | |
- | | + | |
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- | | + | |
- | | + | |
- | end // F=3 | + | |
- | + | ||
- | | + | |
- | end // F=9 | + | |
- | + | ||
- | | + | |
- | if (S1) begin | + | |
- | case (A) | + | |
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- | end // S1=1 | + | |
- | end // F=16 | + | |
- | + | ||
- | | + | |
- | if (S1) begin | + | |
- | case (A) | + | |
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- | end // S1=1 | + | |
- | end // F=17 | + | |
- | + | ||
- | | + | |
- | if (S1) begin | + | |
- | case (A) | + | |
- | | + | |
- | | + | |
- | | + | |
- | | + | |
- | | + | |
- | end // S1=1 | + | |
- | end // F=18 | + | |
- | + | ||
- | | + | |
- | end //N=1 | + | |
- | + | ||
- | end // always Clock | + | |
- | + | ||
- | | + | |
- | if (N) begin | + | |
- | + | ||
- | case (F) | + | |
- | + | ||
- | | + | |
- | X = 1' | + | |
- | Q = 1' | + | |
- | | + | |
- | | + | |
- | | + | |
- | end // F=0 | + | |
- | + | ||
- | | + | |
- | X = 1' | + | |
- | Q = 1' | + | |
- | | + | |
- | | + | |
- | | + | |
- | end // F=1 | + | |
- | + | ||
- | | + | |
- | X = 1' | + | |
- | Q = 1' | + | |
- | | + | |
- | | + | |
- | | + | |
- | end // F=2 | + | |
- | + | ||
- | | + | |
- | X = 1' | + | |
- | Q = 1' | + | |
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- | | + | |
- | | + | |
- | end // F=3 | + | |
- | + | ||
- | | + | |
- | X = 1' | + | |
- | Q = 1' | + | |
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- | | + | |
- | | + | |
- | end // F=9 | + | |
- | + | ||
- | | + | |
- | X = 1' | + | |
- | Q = 1' | + | |
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- | | + | |
- | | + | |
- | end // F=9 | + | |
- | + | ||
- | | + | |
- | X = 1' | + | |
- | Q = 1' | + | |
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- | | + | |
- | | + | |
- | end // F=16 | + | |
- | + | ||
- | | + | |
- | X = 1' | + | |
- | Q = 1' | + | |
- | | + | |
- | | + | |
- | | + | |
- | end // F=17 | + | |
- | + | ||
- | | + | |
- | X = 1' | + | |
- | Q = 1' | + | |
- | | + | |
- | | + | |
- | | + | |
- | end // F=18 | + | |
- | + | ||
- | | + | |
- | | + | |
- | | + | |
- | | + | |
- | X = 1' | + | |
- | Q = 1' | + | |
- | end // default F | + | |
- | + | ||
- | | + | |
- | end // if (N) | + | |
- | + | ||
- | else begin | + | |
- | | + | |
- | | + | |
- | | + | |
- | X = 1' | + | |
- | Q = 1' | + | |
- | end // if (!N) | + | |
- | end // always N or S1 or A or F | + | |
- | + | ||
- | | + | |
- | ===== Time Stamping ===== | + | ====== Time Stamping |
The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger# | The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger# | ||
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Below is the Verilog code of the REGISTERS module of the FPGA configuration, | Below is the Verilog code of the REGISTERS module of the FPGA configuration, | ||
- | | + | ........ |
- | | + | ........ |
- | | + | |
- | | + | |
- | | + | |
- | | + | |
- | | + | |
- | | + | |
- | | + | |
- | | + | |
- | ) ; | + | |
- | + | ||
- | input NSELX ; | + | |
- | input NWRX ; | + | |
- | input ACKX ; | + | |
- | input [20:2] ADRIN ; | + | |
- | input [31:0] DATAIN ; | + | |
- | input [63:0] ScalerA ; | + | |
- | | + | |
- | | + | |
- | | + | |
- | + | ||
- | // add your declarations here | + | |
- | reg Clear; | + | |
- | reg [31:0] DATAOUT; | + | |
- | reg DataDrive; | + | |
- | + | ||
- | | + | |
- | + | ||
- | | + | |
- | | + | |
- | + | ||
- | // Write from VME to FPGA | + | |
- | // Addresses and Data are driven by VME | + | |
- | if (!NSELX & !NWRX & !ACKX) begin | + | |
- | | + | |
- | | + | |
- | case (ADRIN) | + | |
- | 0: Clear = DATAIN[0]; | + | |
- | | + | |
- | end | + | |
- | + | ||
- | // Read from FPGA to VME | + | |
- | // Addresses driven by VME - Data driven by FPGA | + | |
- | else if (!NSELX & NWRX & !ACKX) begin | + | |
- | | + | |
- | case (ADRIN) | + | |
- | 00: DATAOUT = 32' | + | |
- | 01: DATAOUT = ScalerA[31: | + | |
- | 02: DATAOUT = ScalerA[63: | + | |
- | | + | |
- | | + | |
- | end | + | |
- | + | ||
- | // VME not accessing FPGA | + | |
- | else if (NSELX & NWRX & ACKX) begin | + | |
- | | + | |
- | | + | |
- | end | + | |
- | + | ||
- | end | + | |
- | + | ||
- | | + | |
- | + | ||
- | + | ||
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- | ===== Configuration for S800 in tandem with other detectors ===== | + | ====== Configuration for S800 in tandem with other detectors |
In its standard configuration, | In its standard configuration, | ||
To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following: | To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following: | ||
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- | ===== Begin sequence ===== | + | ====== Begin sequence |
The internal " | The internal " | ||
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The last step of the begin sequence allows enough time for the CCUSB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the " | The last step of the begin sequence allows enough time for the CCUSB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the " | ||
- | ===== Scalers and dead time ===== | + | ====== Scalers and dead time ====== |
The " | The " | ||