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-======= Trigger ======= 
 The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors#Plastic scintillators|E1]] and a secondary detector principally located at the target location. This coincidence is often a mandatory requirement when the trigger rate of the S800 alone (S800 singles) is too high for the data acquisition and the resulting dead time is prohibitive.  The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors#Plastic scintillators|E1]] and a secondary detector principally located at the target location. This coincidence is often a mandatory requirement when the trigger rate of the S800 alone (S800 singles) is too high for the data acquisition and the resulting dead time is prohibitive. 
  
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-===== Trigger Schematic =====+====== Trigger Schematic ====== 
 + 
 The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below.  The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. 
  
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 ==== Busy Circuit ==== ==== Busy Circuit ====
 As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The busy circuit following the generation of raw triggers is mainly composed of a latch that is set by the "Raw trigger" signal, and cleared by the falling edge of the OR of the individual busy signals (Busy inputs) coming from individual crate controllers or other data acquisition systems. This way the "Live trigger" signal stays true as long as the longest busy signal. The "Live trigger" signal is therefore a "global busy" signal as well. In addition, the same busy signals of individual crate controllers or other data acquisition system are used to veto the "Raw trigger" signal and prevent the generation of a live trigger. This takes care of situations where separate triggers are generated for some of the crate controllers or other data acquisition systems (such as scaler readout sequences), during which no event readout sequence should be started.  As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The busy circuit following the generation of raw triggers is mainly composed of a latch that is set by the "Raw trigger" signal, and cleared by the falling edge of the OR of the individual busy signals (Busy inputs) coming from individual crate controllers or other data acquisition systems. This way the "Live trigger" signal stays true as long as the longest busy signal. The "Live trigger" signal is therefore a "global busy" signal as well. In addition, the same busy signals of individual crate controllers or other data acquisition system are used to veto the "Raw trigger" signal and prevent the generation of a live trigger. This takes care of situations where separate triggers are generated for some of the crate controllers or other data acquisition systems (such as scaler readout sequences), during which no event readout sequence should be started. 
- 
  
 ==== Time Stamping Scheme ==== ==== Time Stamping Scheme ====
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-===== Trigger module ===== +====== Trigger module ======
 The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/outputs (such as the VME XLM72 module for instance). This section describes the functionality of the S800 trigger module and the commands used to control its parameters.  The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/outputs (such as the VME XLM72 module for instance). This section describes the functionality of the S800 trigger module and the commands used to control its parameters. 
  
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 3  4  Read     Time Stamp (bits 48-63)   3  4  Read     Time Stamp (bits 48-63)  
  
-==== Inputs and outputs ==== 
  
 +==== Inputs and outputs ====
 The following table lists the inputs and outputs to/from the trigger module and their assignment.  The following table lists the inputs and outputs to/from the trigger module and their assignment. 
  
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 Below is the Verilog code used in the configuration for the INTERNAL module:  Below is the Verilog code used in the configuration for the INTERNAL module: 
- module INTERNAL (N, S1, S2, Clock, F, A, Data_in,  +................ 
- DriveRead, Q, X, Data_out,  +....................
- S800Delay, S800Width,  +
- SecondaryDelay, SecondaryWidth,  +
- S800TimingDelay, CoincTimingWidth, +
- SecondaryTimingDelay, Bypasses, +
- S800Factor, SecondaryFactor, TriggerBox, +
- ADCGate, QDCGate, TDCStart, Coincidence, +
- Inspect1, Inspect2, Inspect3, Inspect4, +
- Register, ClearModule, ClearRegister, Go,  +
- TimeStamp, Select, SyncEnable +
- ) ; +
-  +
- input N ; +
- input S1 ; +
- input S2 ; +
- input Clock ; +
- input [4:0] F ; +
- input [3:0] A ; +
- input [23:0] Data_in ; +
- output Q ; +
- output X ; +
- output DriveRead; +
- output [23:0] Data_out ; +
- output [7:0] S800Delay; +
- output [7:0] S800Width ; +
- output [7:0] SecondaryDelay; +
- output [7:0] SecondaryWidth ; +
- output [7:0] S800TimingDelay; +
- output [7:0] CoincTimingWidth ; +
- output [7:0] SecondaryTimingDelay ; +
- output [4:0] Bypasses ; +
- output [9:0] S800Factor ; +
- output [9:0] SecondaryFactor ; +
- output [4:0] TriggerBox ; +
- output [7:0] ADCGate ; +
- output [7:0] QDCGate ; +
- output [7:0] TDCStart ; +
- output [7:0] Coincidence ; +
- output [4:0] Inspect1 ; +
- output [4:0] Inspect2 ; +
- output [4:0] Inspect3 ; +
- output [4:0] Inspect4 ; +
- input [4:0] Register; +
- output ClearModule; +
- output ClearRegister; +
- output Go; +
- input [63:0] TimeStamp; +
- output [1:0] Select; +
- output SyncEnable; +
-  +
- // add your declarations here +
- reg X; +
- reg Q; +
- reg DriveRead ; +
- reg ClearModule; +
- reg ClearRegister; +
- reg Go; +
- reg [1:0] Select; +
- reg SyncEnable; +
- reg [23:0] Data_out ; +
- reg [7:0] S800Delay; +
- reg [7:0] S800Width ; +
- reg [7:0] SecondaryDelay; +
- reg [7:0] SecondaryWidth ; +
- reg [7:0] S800TimingDelay; +
- reg [7:0] CoincTimingWidth ; +
- reg [7:0] SecondaryTimingDelay ; +
- reg [4:0] Bypasses ; +
- reg [9:0] S800Factor ; +
- reg [9:0] SecondaryFactor ; +
- reg [4:0] TriggerBox ; +
- reg [7:0] ADCGate ; +
- reg [7:0] QDCGate ; +
- reg [7:0] TDCStart ; +
- reg [7:0] Coincidence ; +
- reg [4:0] Inspect1 ; +
- reg [4:0] Inspect2 ; +
- reg [4:0] Inspect3 ; +
- reg [4:0] Inspect4 ; +
-  +
- // add your code here +
- always @(posedge Clock) begin +
-   if (N) begin +
-   case (F) +
-     5'd0: begin +
-     case (A) +
-       4'd0: Data_out <= {16'd0, S800Delay}; +
-       4'd1: Data_out <= {16'd0, S800Width}; +
-       4'd2: Data_out <= {16'd0, SecondaryDelay}; +
-       4'd3: Data_out <= {16'd0, SecondaryWidth}; +
-       4'd4: Data_out <= {16'd0, S800TimingDelay}; +
-       4'd5: Data_out <= {16'd0, CoincTimingWidth}; +
-       4'd6: Data_out <= {16'd0, SecondaryTimingDelay}; +
-       4'd7: Data_out <= {19'd0, Bypasses}; +
-       4'd8: Data_out <= {14'd0, S800Factor}; +
-       4'd9: Data_out <= {14'd0, SecondaryFactor}; +
-       4'd10: Data_out <= {19'd0, TriggerBox}; +
-       4'd11: Data_out <= {23'd0, Go}; +
-       4'd12: Data_out <= {22'd0, Select}; +
-       4'd13: Data_out <= {23'd0, SyncEnable}; +
-       4'd14: Data_out <= 24'd5800; +
-       4'd15: Data_out <= 24'd2367; +
-       default: Data_out <= 24'd0; +
-     endcase //A +
-     end // F=0 +
-      +
-     5'd1: begin +
-     case (A) +
-       4'd0: Data_out <= {19'd0, Inspect1}; +
-       4'd1: Data_out <= {19'd0, Inspect2}; +
-       4'd2: Data_out <= {19'd0, Inspect3}; +
-       4'd3: Data_out <= {19'd0, Inspect4}; +
-       default: Data_out <= 24'd0; +
-     endcase //A +
-     end // F=1 +
-      +
-     5'd2: begin +
-     case (A) +
-       4'd0: Data_out <= {16'd0, ADCGate}; +
-       4'd1: Data_out <= {16'd0, QDCGate}; +
-       4'd2: Data_out <= {16'd0, TDCStart}; +
-       4'd3: Data_out <= {16'd0, Coincidence}; +
-       default: Data_out <= 24'd0; +
-     endcase //A +
-     end // F=2 +
-      +
-     5'd3: begin +
-     case (A) +
-       4'd0: Data_out <= {19'd0, Register}; +
-       4'd1: Data_out <= {8'd0, TimeStamp[15:0]}; +
-       4'd2: Data_out <= {8'd0, TimeStamp[31:16]}; +
-       4'd3: Data_out <= {8'd0, TimeStamp[47:32]}; +
-       4'd4: Data_out <= {8'd0, TimeStamp[63:48]}; +
-       default: Data_out <= 24'd0; +
-     endcase //A +
-     end // F=3 +
-      +
-     5'd9: begin +
-     end // F=9 +
-  +
-     5'd16: begin +
-     if (S1) begin +
-       case (A) +
-       4'd0: S800Delay <= Data_in[7:0]; +
-       4'd1: S800Width <= Data_in[7:0]; +
-       4'd2: SecondaryDelay <= Data_in[7:0]; +
-       4'd3: SecondaryWidth <= Data_in[7:0]; +
-       4'd4: S800TimingDelay <= Data_in[7:0]; +
-       4'd5: CoincTimingWidth <= Data_in[7:0]; +
-       4'd6: SecondaryTimingDelay <= Data_in[7:0]; +
-       4'd7: Bypasses <= Data_in[4:0]; +
-       4'd8: S800Factor <= Data_in[9:0]; +
-       4'd9: SecondaryFactor <= Data_in[9:0]; +
-       4'd10: TriggerBox <= Data_in[4:0]; +
-       4'd11: Go <= Data_in[0:0]; +
-       4'd12: Select <= Data_in[1:0]; +
-       4'd13: SyncEnable <= Data_in[0:0]; +
-       endcase //A +
-     end // S1=1 +
-     end // F=16 +
-        +
-     5'd17: begin +
-     if (S1) begin +
-       case (A) +
-         4'd0: Inspect1 <= Data_in[4:0]; +
-         4'd1: Inspect2 <= Data_in[4:0]; +
-         4'd2: Inspect3 <= Data_in[4:0]; +
-         4'd3: Inspect4 <= Data_in[4:0]; +
-       endcase //A +
-     end // S1=1 +
-     end // F=17 +
-        +
-     5'd18: begin +
-     if (S1) begin +
-       case (A) +
-         4'd0: ADCGate <= Data_in[7:0]; +
-         4'd1: QDCGate <= Data_in[7:0]; +
-         4'd2: TDCStart <= Data_in[7:0]; +
-         4'd3: Coincidence <= Data_in[7:0]; +
-       endcase //A +
-     end // S1=1 +
-     end // F=18 +
-       +
-   endcase // F +
-   end //N=1 +
-  +
- end // always Clock +
-  +
- always @(N or S1 or F or A) begin +
-   if (N) begin +
-    +
-   case (F) +
-    +
-   5'd0: begin +
-     X = 1'b1; +
-     Q = 1'b1; +
-     DriveRead = 1'b1; +
-     ClearModule = 1'b0; +
-     ClearRegister = 1'b0; +
-   end // F=0 +
-  +
-   5'd1: begin +
-     X = 1'b1; +
-     Q = 1'b1; +
-     DriveRead = 1'b1; +
-     ClearModule = 1'b0; +
-     ClearRegister = 1'b0; +
-   end // F=1 +
-  +
-   5'd2: begin +
-     X = 1'b1; +
-     Q = 1'b1; +
-     DriveRead = 1'b1; +
-     ClearModule = 1'b0; +
-     ClearRegister = 1'b0; +
-   end // F=2 +
-  +
-   5'd3: begin +
-     X = 1'b1; +
-     Q = 1'b1; +
-     DriveRead = 1'b1; +
-     ClearModule = 1'b0; +
-     ClearRegister = 1'b0; +
-   end // F=3 +
-  +
-   5'd9: begin +
-     X = 1'b1; +
-     Q = 1'b1; +
-     DriveRead = 1'b0; +
-     ClearModule = 1'b1; +
-     ClearRegister = 1'b0; +
-   end // F=9 +
-  +
-   5'd10: begin +
-     X = 1'b1; +
-     Q = 1'b1; +
-     DriveRead = 1'b0; +
-     ClearModule = 1'b0; +
-     ClearRegister = 1'b1; +
-   end // F=9 +
-  +
-   5'd16: begin +
-     X = 1'b1; +
-     Q = 1'b1; +
-     DriveRead = 1'b0; +
-     ClearModule = 1'b0; +
-     ClearRegister = 1'b0; +
-   end // F=16 +
-    +
-   5'd17: begin +
-     X = 1'b1; +
-     Q = 1'b1; +
-     DriveRead = 1'b0; +
-     ClearModule = 1'b0; +
-     ClearRegister = 1'b0; +
-   end // F=17 +
-    +
-   5'd18: begin +
-     X = 1'b1; +
-     Q = 1'b1; +
-     DriveRead = 1'b0; +
-     ClearModule = 1'b0; +
-     ClearRegister = 1'b0; +
-   end // F=18 +
-    +
-   default: begin +
-     DriveRead = 1'b0;  +
-     ClearModule = 1'b0; +
-     ClearRegister = 1'b0; +
-     X = 1'b0; +
-     Q = 1'b0; +
-   end // default F +
-  +
-   endcase // F +
-   end // if (N) +
-    +
-   else begin +
-   DriveRead = 1'b0; +
-   ClearModule = 1'b0; +
-   ClearRegister = 1'b0; +
-   X = 1'b0; +
-   Q = 1'b0; +
-   end // if (!N) +
- end // always N or S1 or A or F +
-  +
- endmodule+
  
  
  
  
-===== Time Stamping =====+====== Time Stamping ======
 The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger#Trigger Schematic|GUI]]). The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section on [[begin sequence]]). The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized.  The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger#Trigger Schematic|GUI]]). The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section on [[begin sequence]]). The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized. 
  
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 Below is the Verilog code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME bus:  Below is the Verilog code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME bus: 
- module Registers ( +........ 
- NSELX, +........
- NWRX, +
- ACKX, +
- ADRIN, +
- DATAIN, +
- DATAOUT, +
- DataDrive, +
- Clear, +
- ScalerA +
- ) ; +
-  +
- input NSELX ; +
- input NWRX ; +
- input ACKX ; +
- input [20:2] ADRIN ; +
- input [31:0] DATAIN ; +
- input [63:0] ScalerA ; +
- output [31:0] DATAOUT ; +
- output Clear ; +
- output DataDrive; +
-  +
- // add your declarations here +
- reg Clear; +
- reg [31:0] DATAOUT; +
- reg DataDrive; +
-  +
- always @(NSELX or NWRX or ACKX or DATAIN or ADRIN) begin +
-  +
-   DataDrive = 0; +
-   DATAOUT = 32'd0; +
-  +
- // Write from VME to FPGA +
- // Addresses and Data are driven by VME +
-   if (!NSELX & !NWRX & !ACKX) begin +
-   DataDrive = 0; +
-   DATAOUT = 32'd0; +
-   case (ADRIN) +
-     0: Clear = DATAIN[0]; +
-   endcase //ADRIN +
-   end +
-  +
- // Read from FPGA to VME +
- // Addresses driven by VME - Data driven by FPGA +
-   else if (!NSELX & NWRX & !ACKX) begin +
-   DataDrive = 1; +
-   case (ADRIN) +
-     00: DATAOUT = 32'hDABA0002; +
-     01: DATAOUT = ScalerA[31:0]; +
-     02: DATAOUT = ScalerA[63:32]; +
-     default: DATAOUT = 32'd0; +
-   endcase +
-   end +
-  +
- // VME not accessing FPGA +
-   else if (NSELX & NWRX & ACKX) begin +
-   DataDrive = 1; +
-   DATAOUT = 32'd0; +
-   end +
-    +
- end +
-  +
- endmodule +
- +
- +
  
  
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-===== Configuration for S800 in tandem with other detectors =====+====== Configuration for S800 in tandem with other detectors ======
 In its standard configuration, the S800 data acquisition uses one CAMAC crate and one VME crate only. The CC-USB and VM-USB crate controller modules performing the readout are connected to the latches number 1 and 2 of the trigger module, respectively. Each crate controller is configured to output their busy and end-of-event signals on their available NIM outputs, which are then connected to the appropriate inputs on the trigger module.  In its standard configuration, the S800 data acquisition uses one CAMAC crate and one VME crate only. The CC-USB and VM-USB crate controller modules performing the readout are connected to the latches number 1 and 2 of the trigger module, respectively. Each crate controller is configured to output their busy and end-of-event signals on their available NIM outputs, which are then connected to the appropriate inputs on the trigger module. 
 To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following:  To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following: 
Line 528: Line 177:
  
  
-===== Begin sequence =====+====== Begin sequence ======
 The internal "Go" state of the trigger module is controlled via CAMAC commands. When "Go" is false, the trigger and time stamp clock signals are vetoed and therefore absent. This way all time stamp counters can be safely zeroed during the beginning sequence of the data acquisition systems. The last command of the CAMAC beginning sequence sets the "Go" state to true, at which point both trigger and time stamp signals are released. This mechanism ensures that all time stamp counters are synchronized.  The internal "Go" state of the trigger module is controlled via CAMAC commands. When "Go" is false, the trigger and time stamp clock signals are vetoed and therefore absent. This way all time stamp counters can be safely zeroed during the beginning sequence of the data acquisition systems. The last command of the CAMAC beginning sequence sets the "Go" state to true, at which point both trigger and time stamp signals are released. This mechanism ensures that all time stamp counters are synchronized. 
  
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 The last step of the begin sequence allows enough time for the CCUSB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the "Go" state of the module back to false.  The last step of the begin sequence allows enough time for the CCUSB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the "Go" state of the module back to false. 
  
-===== Scalers and dead time =====+====== Scalers and dead time ======
 The "D" connector of the trigger module is directly connected to 16 inputs of a scaler module (see mapping in the inputs and outputs section below). Scalers are connected to each of the trigger source inputs, as well as trigger box inputs. These scalers can be used to recover the number of trigger signals occurring on each of the source and trigger box inputs, in addition to the information coded for each event in the trigger register.  The "D" connector of the trigger module is directly connected to 16 inputs of a scaler module (see mapping in the inputs and outputs section below). Scalers are connected to each of the trigger source inputs, as well as trigger box inputs. These scalers can be used to recover the number of trigger signals occurring on each of the source and trigger box inputs, in addition to the information coded for each event in the trigger register. 
  
trigger.txt · Last modified: 2023/10/24 16:47 by swartzj

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