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trigger [2013/12/10 21:32] pereira |
trigger [2013/12/11 14:41] pereira [Time Stamping Scheme] |
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- Direct visualization of the trigger logic and configuration | - Direct visualization of the trigger logic and configuration | ||
- | Probably the most appealing feature of this module is the possibility to remotely control the trigger timing and configuration while beam is present in the vault, since most experiments are nowadays locating their electronics close to the detectors. | + | Probably the most appealing feature of this module is the possibility to remotely control the trigger timing and configuration while beam is present in the vault, since most experiments are nowadays locating their electronics close to the detectors. For more details on this detector check section [[Trigger# |
- | The S800 trigger from the [[Detectors# | ||
- | ====== Trigger | + | The S800 trigger from the [[Detectors# |
+ | |||
+ | |||
+ | ===== Trigger | ||
The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | ||
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- | ===== Trigger | + | ==== Trigger |
In addition to the singles and coincidence triggers, two separate trigger sources labeled " | In addition to the singles and coincidence triggers, two separate trigger sources labeled " | ||
- | Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" | + | Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" |
- | More details about the trigger box module and its FPGA schematics can be found [[here]]. | + | More details about the trigger box module and its FPGA schematics can be found in section |
- | ===== Gate generation | + | ==== Gate generation ==== |
All digitizer gates and start signals are derived from the live trigger signal, with the exception of the QDC gate which is directly generated from the S800 source signal. The reason is to avoid long analog delays on the scintillator signals. A fast clear circuit is provided to clear the QDC if no valid trigger was generated. | All digitizer gates and start signals are derived from the live trigger signal, with the exception of the QDC gate which is directly generated from the S800 source signal. The reason is to avoid long analog delays on the scintillator signals. A fast clear circuit is provided to clear the QDC if no valid trigger was generated. | ||
- | ===== Inspect channels | + | ==== Inspect channels ==== |
A set of four inspect channels are patched out to the Data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit. | A set of four inspect channels are patched out to the Data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit. | ||
- | ===== Busy Circuit | + | ==== Busy Circuit ==== |
As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The busy circuit following the generation of raw triggers is mainly composed of a latch that is set by the "Raw trigger" | As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The busy circuit following the generation of raw triggers is mainly composed of a latch that is set by the "Raw trigger" | ||
- | + | ==== Time Stamping Scheme ==== | |
- | ===== Time Stamping Scheme | + | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping schemes are incorporated in the trigger to synchronize events. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward. More details about the time stamping |
- | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping | + | |
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The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/ | The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/ | ||
- | ===== CAMAC commands | + | ==== CAMAC commands ==== |
The following table lists the CAMAC codes recognized by the trigger module and their signification. | The following table lists the CAMAC codes recognized by the trigger module and their signification. | ||
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- | ===== Inputs and outputs | + | ==== Inputs and outputs ==== |
The following table lists the inputs and outputs to/from the trigger module and their assignment. | The following table lists the inputs and outputs to/from the trigger module and their assignment. | ||
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B16 (out) Time stamp clock C16 (out) D16 (out) 1 Hz | B16 (out) Time stamp clock C16 (out) D16 (out) 1 Hz | ||
- | ===== FPGA firmware | + | ==== FPGA firmware ==== |
The firmware of the trigger module is shown in the following files. The PDF file contains the schematic sheets, used for most of the design. The Verilog file contains the block dealing with CAMAC communications. | The firmware of the trigger module is shown in the following files. The PDF file contains the schematic sheets, used for most of the design. The Verilog file contains the block dealing with CAMAC communications. | ||
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- | ====== Time Stamping | + | ====== Time stamping |
The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger# | The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger# | ||
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The last step of the begin sequence allows enough time for the CCUSB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the " | The last step of the begin sequence allows enough time for the CCUSB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the " | ||
- | ===== Scalers and dead time ===== | + | ====== Scalers and dead time ====== |
- | The " | + | The " |
In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger. | In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger. |