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trigger [2013/12/10 21:32] pereira |
trigger [2013/12/26 13:20] pereira [Trigger] |
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- | The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors# | + | ====== Trigger ====== |
- | The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. The main motivations for implementing the trigger logic in an FPGA driven module are the following: | + | |
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | |||
+ | |||
+ | The main purpose of the trigger is to implement a coincidence between the S800 focal-plane [[Detectors# | ||
+ | |||
+ | The trigger logic is implemented in a {{: | ||
- Simplify cabling and setup of the trigger | - Simplify cabling and setup of the trigger | ||
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- Direct visualization of the trigger logic and configuration | - Direct visualization of the trigger logic and configuration | ||
- | Probably the most appealing feature of this module is the possibility to remotely control the trigger timing and configuration while beam is present in the vault, since most experiments are nowadays locating their electronics close to the detectors. | + | Probably the most appealing feature of this module is the possibility to remotely control the trigger timing and configuration while beam is present in the vault, since most experiments are nowadays locating their electronics close to the detectors. |
- | The S800 trigger from the [[Detectors# | ||
+ | The S800 trigger from the [[Detectors# | ||
- | ====== Trigger | + | ===== Trigger |
The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | ||
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- | ===== Trigger | + | ==== Trigger |
In addition to the singles and coincidence triggers, two separate trigger sources labeled " | In addition to the singles and coincidence triggers, two separate trigger sources labeled " | ||
- | Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" | + | Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" |
- | More details about the trigger box module and its FPGA schematics can be found [[here]]. | + | More details about the trigger box module and its FPGA schematics can be found in section "[[Trigger# |
- | ===== Gate generation | + | ==== Gate generation ==== |
All digitizer gates and start signals are derived from the live trigger signal, with the exception of the QDC gate which is directly generated from the S800 source signal. The reason is to avoid long analog delays on the scintillator signals. A fast clear circuit is provided to clear the QDC if no valid trigger was generated. | All digitizer gates and start signals are derived from the live trigger signal, with the exception of the QDC gate which is directly generated from the S800 source signal. The reason is to avoid long analog delays on the scintillator signals. A fast clear circuit is provided to clear the QDC if no valid trigger was generated. | ||
- | ===== Inspect channels | + | ==== Inspect channels ==== |
A set of four inspect channels are patched out to the Data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit. | A set of four inspect channels are patched out to the Data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit. | ||
- | ===== Busy Circuit | + | ==== Busy Circuit ==== |
As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The busy circuit following the generation of raw triggers is mainly composed of a latch that is set by the "Raw trigger" | As each controller and external data acquisition perform their readout sequence in parallel, they have different busy times. The busy circuit following the generation of raw triggers is mainly composed of a latch that is set by the "Raw trigger" | ||
+ | ==== Time Stamping Scheme ==== | ||
+ | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping schemes are incorporated in the trigger to synchronize events. Because of this modularity, the same synchronization scheme can be used when coupling external data acquisition systems to the S800. | ||
- | ===== Time Stamping Scheme ===== | ||
- | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping and busy schemes are incorporated in the trigger to synchronize events and insure no trigger is generated while readout sequences are being executed. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward. More details about the time stamping can be found [[Trigger# | ||
+ | More details about the time stamping module can be found in section " | ||
- | ====== Trigger module | + | ===== Trigger module ===== |
- | The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/ | + | The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/ |
- | ===== CAMAC commands | + | ==== CAMAC commands ==== |
- | The following | + | A table with the list of the CAMAC commands |
- | F A Direction | ||
- | 0 0 Read 16 0 Write S800 Gate & Delay (delay) | ||
- | 0 1 Read 16 1 Write S800 Gate & Delay (width) | ||
- | 0 2 Read 16 2 Write Secondary Gate & Delay (delay) | ||
- | 0 3 Read 16 3 Write Secondary Gate & Delay (width) | ||
- | 0 4 Read 16 4 Write S800 Delay (delay) | ||
- | 0 5 Read 16 5 Write Coincidence Gate (width) | ||
- | 0 6 Read 16 6 Write Secondary Delay (delay) | ||
- | 0 7 Read 16 7 Write Bypasses (bit pattern) | ||
- | 0 8 Read 16 8 Write S800 Downscaler (factor) | ||
- | 0 9 Read 16 9 Write Secondary Downscaler (factor) | ||
- | 0 10 Read 16 10 Write Trigger Box (bit pattern) | ||
- | 0 11 Read 16 11 Write Go signal (bit) | ||
- | 0 12 Read 16 12 Write External Time Stamp Clock (bit 0) | ||
- | and External Time Stamp Latch (bit 1) | ||
- | |||
- | 0 14 Read | ||
- | 0 15 Read | ||
- | 1 0 Read 17 0 Write Inspect Channel 1 (wire) | ||
- | 1 1 Read 17 1 Write Inspect Channel 2 (wire) | ||
- | 1 2 Read 17 2 Write Inspect Channel 3 (wire) | ||
- | 1 3 Read 17 3 Write Inspect Channel 4 (wire) | ||
- | 2 0 Read 18 0 Write ADC Gate (width) | ||
- | 2 1 Read 18 1 Write QDC Gate (width) | ||
- | 2 2 Read 18 2 Write TDC Gate (width) | ||
- | 2 3 Read 18 3 Write Coincidence Register Gate (width) | ||
- | 3 0 Read | ||
- | 3 1 Read Time Stamp (bits 0-15) | ||
- | 3 2 Read Time Stamp (bits 16-31) | ||
- | 3 3 Read Time Stamp (bits 32-47) | ||
- | 3 4 Read Time Stamp (bits 48-63) | ||
+ | ==== Inputs and outputs ==== | ||
+ | A table with the list of inputs/ | ||
- | ===== Inputs and outputs ===== | + | ==== FPGA firmware |
- | The following table lists the inputs and outputs to/ | + | The firmware of the trigger module |
- | Pin Assignment | ||
- | A1 (in) S800 source | ||
- | A2 (in) Secondary source | ||
- | A3 (in) External 1 source | ||
- | A4 (in) External 2 source | ||
- | A5 (in) Clear busy B5 (out) TDC start C5 (in) Busy 5 D5 (out) S800 trigger | ||
- | A6 (in) Clear module | ||
- | A7 (in) Gretina sync B7 (out) C7 (in) Busy 7 D7 (out) External 1 trigger | ||
- | A8 (in) Time stamp clock B8 (out) Live trigger | ||
- | B9 (out) Inspect 1 C9 (out) Time stamp clock D9 (out) Secondary trigger | ||
- | B10 (out) Inspect 2 C10 (out) Time stamp latch D10 (out) Raw trigger | ||
- | B11 (out) Inspect 3 C11 (out) D11 (out) Live trigger | ||
- | B12 (out) Inspect 4 C12 (out) D12 (out) Raw pulser | ||
- | B13 (out) Fast clear C13 (out) D13 (out) Live pulser | ||
- | B14 (out) C14 (out) D14 (out) Fast clear | ||
- | B15 (out) Go C15 (out) D15 (out) 10 Hz | ||
- | B16 (out) Time stamp clock C16 (out) D16 (out) 1 Hz | ||
- | ===== FPGA firmware | + | ====== Time stamping ====== |
- | The firmware of the trigger | + | The S800 trigger |
- | File containing | + | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. |
- | Below is the Verilog code used in the configuration for the INTERNAL module: | ||
- | ................ | ||
- | .................... | ||
+ | The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available {{: | ||
- | |||
- | |||
- | ====== Time Stamping ====== | ||
- | The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger# | ||
- | |||
- | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available [{{: | ||
E1: time stamp clock input | E1: time stamp clock input | ||
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The clear can be done via software as well, and is usually done that way. | The clear can be done via software as well, and is usually done that way. | ||
- | Below is the Verilog | + | The [[Verilog Time stamping|Verilog file]] contains |
- | ........ | + | |
- | ........ | + | |
- | + | ||
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====== Begin sequence ====== | ====== Begin sequence ====== | ||
- | The internal " | + | The internal " |
- | The data acquisition begin sequence of the trigger module is the following: | + | The data acquisition begin sequence of the trigger module is the following: |
- | reset time stamp counter to 0 | + | |
- | reset trigger register to 0 | + | |
- | after all modules in all crates have been initialized, | + | |
- | after a preset delay of 200 to 300 microseconds, | + | |
+ | |||
+ | The last step of the begin sequence allows enough time for the CC-USB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the " | ||
- | The last step of the begin sequence allows enough time for the CCUSB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the " | + | ====== Scalers and dead time ====== |
- | + | The " | |
- | ===== Scalers and dead time ===== | + | |
- | The " | + | |
In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger. | In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger. | ||
+ | The list below is a direct copy of the scaler description file for the s800. This file maps channel names to channel numbers, and in addition determines the layout. | ||
+ | |||
+ | ^ Channel name ^ Channel number ^ Channel name ^ Channel number | | ||
+ | | Live.Trigger | ||
+ | | Live.Clock | ||
+ | | S800.Source | ||
+ | | Second.Source ^ 1 | Second.Trigger ^ 8 | | ||
+ | | Ext1.Source | ||
+ | | Ext2.Source | ||
+ | | Coinc.Trigger ^ 5 | ^ | | ||
+ | | E1.Up ^ 16 | E1.Down | ||
+ | | E2.Up ^ 18 | E2.Down | ||
+ | | CRDC1.Anode | ||
+ | | TPPAC1 | ||
+ | | OBJ.Scint | ||
+ | | TAR.Scint | ||
+ | | S800.Source | ||
+ | | S800.Source | ||
+ | | S800.Source | ||
+ | | Hodo.OR | ||