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--- trigger [2013/12/11 14:14]
pereira [Trigger Box]
+++ trigger [2013/12/11 14:22]
pereira
@@ Line 9: / Line 9: @@
   - Direct visualization of the trigger logic and configuration
-Probably the most appealing feature of this module is the possibility to remotely control the trigger timing and configuration while beam is present in the vault, since most experiments are nowadays locating their electronics close to the detectors.
+Probably the most appealing feature of this module is the possibility to remotely control the trigger timing and configuration while beam is present in the vault, since most experiments are nowadays locating their electronics close to the detectors. For more details on this detector check section [[Trigger#Trigger module|Trigger module]].
-The S800 trigger from the [[Detectors#Plastic scintillators|E1 scintillator]] provides also the reference time for the [[Detectors#Cathode Readout Drift Chambers (CRDC)|CRDCs]] as well as time-of-flight measurements. Note that because the FPGA uses a 40 MHz internal clock, the time reference of the signals in the trigger circuit are set the phase of that clock, and therefore jitter by 25 ns with respect to the source signals. This jitter is measured with a TDC and can be subtracted to the time measurements to recover the timing relative to the source signals.
-====== Trigger Schematic ======
+The S800 trigger from the [[Detectors#Plastic scintillators|E1 scintillator]] provides also the reference time for the [[Detectors#Cathode Readout Drift Chambers (CRDC)|CRDCs]] as well as time-of-flight measurements. Note that because the FPGA uses a 40 MHz internal clock, the time reference of the signals in the trigger circuit set the phase of that clock, and therefore jitter by 25 ns with respect to the source signals. This jitter is measured with a TDC and can be subtracted to the time measurements to recover the timing relative to the source signals.
+=Trigger schematic=
 The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below.
@@ Line 28: / Line 30: @@
 Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" output of the trigger box may generate two pulses for a single event. A scaler connected to the "Raw trigger" output will therefore not reflect the true number of events. For this reason scalers are also connected to individual inputs of the trigger box (for more details, check the section [[Trigger#Scalers and dead time|Scalers and dead time]]). A trigger register word (bit pattern) is written at each occurrence of a live trigger signal. This word is the first being read out from the trigger module, prior to the time stamp ([[check trigger packet tag 0x2367 in the DAQ section for more information]]).
-More details about the trigger box module and its FPGA schematics can be found in section [[Trigger#Trigger Module|Trigger Module]].
+More details about the trigger box module and its FPGA schematics can be found in section [[Trigger#Trigger module|Trigger module]].

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