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trigger [2013/12/11 14:43] pereira [Time Stamping Scheme] |
trigger [2013/12/11 15:08] pereira [CAMAC commands] |
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- | ====== Trigger module | + | ===== Trigger module ===== |
The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/ | The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/ | ||
+ | |||
+ | ==== CAMAC commands ==== | ||
+ | |||
+ | The following table lists the CAMAC codes recognized by the trigger module and their signification. | ||
+ | |||
+ | |||
+ | ^ F ^ A ^ Direction ^ F ^ A ^ Direction ^ Data ^ | ||
+ | | 0 | 0 | Read | 16 | 0 | Write | S800 Gate & Delay (delay) | | ||
+ | | 0 | 1 | Read | 16 | 1 | Write | S800 Gate & Delay (width) | | ||
+ | | 0 | 2 | Read | 16 | 2 | Write | Secondary Gate & Delay (delay) | | ||
+ | | 0 | 3 | Read | 16 | 3 | Write | Secondary Gate & Delay (width) | | ||
+ | | 0 | 4 | Read | 16 | 4 | Write | S800 Delay (delay) | | ||
+ | | 0 | 5 | Read | 16 | 5 | Write | Coincidence Gate (width) | | ||
+ | | 0 | 6 | Read | 16 | 6 | Write | Secondary Delay (delay) | | ||
+ | | 0 | 7 | Read | 16 | 7 | Write | Bypasses (bit pattern) | | ||
+ | | 0 | 8 | Read | 16 | 8 | Write | S800 Downscaler (factor) | | ||
+ | | 0 | 9 | Read | 16 | 9 | Write | Secondary Downscaler (factor) | | ||
+ | | 0 | 10 | Read | 16 | 10 | Write | Trigger Box (bit pattern) | | ||
+ | | 0 | 11 | Read | 16 | 11 | Write | Go signal (bit) | | ||
+ | | 0 | 12 | Read | 16 | 12 | Write | External Time Stamp Clock (bit 0)and External Time Stamp Latch (bit 1) | | ||
+ | | 0 | 14 | Read | | | | Signature 1 (0x5800) | | ||
+ | | 0 | 15 | Read | | | | Signature 2 (0x2367) | | ||
+ | | 1 | 0 | Read | 17 | 0 | Write | Inspect Channel 1 (wire) | | ||
+ | | 1 | 1 | Read | 17 | 1 | Write | Inspect Channel 2 (wire) | | ||
+ | | 1 | 2 | Read | 17 | 2 | Write | Inspect Channel 3 (wire) | | ||
+ | | 1 | 3 | Read | 17 | 3 | Write | Inspect Channel 4 (wire) | | ||
+ | | 2 | 0 | Read | 18 | 0 | Write | ADC Gate (width) | | ||
+ | | 2 | 1 | Read | 18 | 1 | Write | QDC Gate (width) | | ||
+ | | 2 | 2 | Read | 18 | 2 | Write | TDC Gate (width) | | ||
+ | | 2 | 3 | Read | 18 | 3 | Write | Coincidence Register Gate (width) | | ||
+ | | 3 | 0 | Read | | | | Trigger Box Register (bit pattern) | | ||
+ | | 3 | 1 | Read | | | | Time Stamp (bits 0-15) | | ||
+ | | 3 | 2 | Read | | | | Time Stamp (bits 16-31) | | ||
+ | | 3 | 3 | Read | | | | Time Stamp (bits 32-47) | | ||
+ | | 3 | 4 | Read | | | | Time Stamp (bits 48-63) | | ||
+ | |||
+ | ==Inputs and outputs== | ||
+ | The following table lists the inputs and outputs to/from the trigger module and their assignment. | ||
+ | |||
+ | {| class=" | ||
+ | | Pin | ||
+ | | Assignment | ||
+ | | Pin | ||
+ | | Assignment | ||
+ | | Pin | ||
+ | | Assignment | ||
+ | | Pin | ||
+ | | Assignment | ||
+ | |- | ||
+ | | A1 (in) | ||
+ | | S800 source | ||
+ | | B1 (out) | ||
+ | | Raw trigger | ||
+ | | C1 (in) | ||
+ | | Busy 1 | ||
+ | | D1 (out) | ||
+ | | S800 source | ||
+ | |- | ||
+ | | A2 (in) | ||
+ | | Secondary source | ||
+ | | B2 (out) | ||
+ | | Live trigger | ||
+ | | C2 (in) | ||
+ | | Busy 2 | ||
+ | | D2 (out) | ||
+ | | Secondary source | ||
+ | |- | ||
+ | | A3 (in) | ||
+ | | External 1 source | ||
+ | | B3 (out) | ||
+ | | ADC gate | ||
+ | | C3 (in) | ||
+ | | Busy 3 | ||
+ | | D3 (out) | ||
+ | | External 1 source | ||
+ | |- | ||
+ | | A4 (in) | ||
+ | | External 2 source | ||
+ | | B4 (out) | ||
+ | | QDC gate | ||
+ | | C4 (in) | ||
+ | | Busy 4 | ||
+ | | D4 (out) | ||
+ | | External 2 source | ||
+ | |- | ||
+ | | A5 (in) | ||
+ | | Clear busy | ||
+ | | B5 (out) | ||
+ | | TDC start | ||
+ | | C5 (in) | ||
+ | | Busy 5 | ||
+ | | D5 (out) | ||
+ | | S800 trigger | ||
+ | |- | ||
+ | | A6 (in) | ||
+ | | Clear module | ||
+ | | B6 (out) | ||
+ | | Trigger register gate | ||
+ | | C6 (in) | ||
+ | | Busy 6 | ||
+ | | D6 (out) | ||
+ | | Coincidence trigger | ||
+ | |- | ||
+ | | A7 (in) | ||
+ | | Gretina sync | ||
+ | | B7 (out) | ||
+ | | | ||
+ | | C7 (in) | ||
+ | | Busy 7 | ||
+ | | D7 (out) | ||
+ | | External 1 trigger | ||
+ | |- | ||
+ | | A8 (in) | ||
+ | | Time stamp clock | ||
+ | | B8 (out) | ||
+ | | Live trigger | ||
+ | | C8 (in) | ||
+ | | Time stamp latch | ||
+ | | D8 (out) | ||
+ | | External 2 trigger | ||
+ | |- | ||
+ | | | ||
+ | | | ||
+ | | B9 (out) | ||
+ | | Inspect 1 | ||
+ | | C9 (out) | ||
+ | | Time stamp clock | ||
+ | | D9 (out) | ||
+ | | Secondary trigger | ||
+ | |- | ||
+ | | | ||
+ | | | ||
+ | | B10 (out) | ||
+ | | Inspect 2 | ||
+ | | C10 (out) | ||
+ | | Time stamp latch | ||
+ | | D10 (out) | ||
+ | | Raw trigger | ||
+ | |- | ||
+ | | | ||
+ | | | ||
+ | | B11 (out) | ||
+ | | Inspect 3 | ||
+ | | C11 (out) | ||
+ | | | ||
+ | | D11 (out) | ||
+ | | Live trigger | ||
+ | |- | ||
+ | | | ||
+ | | | ||
+ | | B12 (out) | ||
+ | | Inspect 4 | ||
+ | | C12 (out) | ||
+ | | | ||
+ | | D12 (out) | ||
+ | | Raw pulser | ||
+ | |- | ||
+ | | | ||
+ | | | ||
+ | | B13 (out) | ||
+ | | Fast clear | ||
+ | | C13 (out) | ||
+ | | | ||
+ | | D13 (out) | ||
+ | | Live pulser | ||
+ | |- | ||
+ | | | ||
+ | | | ||
+ | | B14 (out) | ||
+ | | | ||
+ | | C14 (out) | ||
+ | | | ||
+ | | D14 (out) | ||
+ | | Fast clear | ||
+ | |- | ||
+ | | | ||
+ | | | ||
+ | | B15 (out) | ||
+ | | Go | ||
+ | | C15 (out) | ||
+ | | | ||
+ | | D15 (out) | ||
+ | | 10 Hz | ||
+ | |- | ||
+ | | | ||
+ | | | ||
+ | | B16 (out) | ||
+ | | Time stamp clock | ||
+ | | C16 (out) | ||
+ | | | ||
+ | | D16 (out) | ||
+ | | 1 Hz | ||
+ | |} | ||
+ | |||
+ | ==FPGA firmware== | ||
+ | The firmware of the trigger module is shown in the following files. The PDF file contains the schematic sheets, used for most of the design. The Verilog file contains the block dealing with CAMAC communications. | ||
+ | |||
+ | File containing the schematics: [[File: | ||
+ | |||
+ | Below is the Verilog code used in the configuration for the INTERNAL module: | ||
+ | |||
+ | module INTERNAL (N, S1, S2, Clock, F, A, Data_in, | ||
+ | DriveRead, Q, X, Data_out, | ||
+ | S800Delay, S800Width, | ||
+ | SecondaryDelay, | ||
+ | S800TimingDelay, | ||
+ | SecondaryTimingDelay, | ||
+ | S800Factor, SecondaryFactor, | ||
+ | ADCGate, QDCGate, TDCStart, Coincidence, | ||
+ | Inspect1, Inspect2, Inspect3, Inspect4, | ||
+ | Register, ClearModule, | ||
+ | TimeStamp, Select, SyncEnable | ||
+ | ) ; | ||
+ | | ||
+ | input N ; | ||
+ | input S1 ; | ||
+ | input S2 ; | ||
+ | input Clock ; | ||
+ | input [4:0] F ; | ||
+ | input [3:0] A ; | ||
+ | input [23:0] Data_in ; | ||
+ | output Q ; | ||
+ | output X ; | ||
+ | output DriveRead; | ||
+ | output [23:0] Data_out ; | ||
+ | output [7:0] S800Delay; | ||
+ | output [7:0] S800Width ; | ||
+ | output [7:0] SecondaryDelay; | ||
+ | output [7:0] SecondaryWidth ; | ||
+ | output [7:0] S800TimingDelay; | ||
+ | output [7:0] CoincTimingWidth ; | ||
+ | output [7:0] SecondaryTimingDelay ; | ||
+ | output [4:0] Bypasses ; | ||
+ | output [9:0] S800Factor ; | ||
+ | output [9:0] SecondaryFactor ; | ||
+ | output [4:0] TriggerBox ; | ||
+ | output [7:0] ADCGate ; | ||
+ | output [7:0] QDCGate ; | ||
+ | output [7:0] TDCStart ; | ||
+ | output [7:0] Coincidence ; | ||
+ | output [4:0] Inspect1 ; | ||
+ | output [4:0] Inspect2 ; | ||
+ | output [4:0] Inspect3 ; | ||
+ | output [4:0] Inspect4 ; | ||
+ | input [4:0] Register; | ||
+ | output ClearModule; | ||
+ | output ClearRegister; | ||
+ | output Go; | ||
+ | input [63:0] TimeStamp; | ||
+ | output [1:0] Select; | ||
+ | output SyncEnable; | ||
+ | | ||
+ | // add your declarations here | ||
+ | reg X; | ||
+ | reg Q; | ||
+ | reg DriveRead ; | ||
+ | reg ClearModule; | ||
+ | reg ClearRegister; | ||
+ | reg Go; | ||
+ | reg [1:0] Select; | ||
+ | reg SyncEnable; | ||
+ | reg [23:0] Data_out ; | ||
+ | reg [7:0] S800Delay; | ||
+ | reg [7:0] S800Width ; | ||
+ | reg [7:0] SecondaryDelay; | ||
+ | reg [7:0] SecondaryWidth ; | ||
+ | reg [7:0] S800TimingDelay; | ||
+ | reg [7:0] CoincTimingWidth ; | ||
+ | reg [7:0] SecondaryTimingDelay ; | ||
+ | reg [4:0] Bypasses ; | ||
+ | reg [9:0] S800Factor ; | ||
+ | reg [9:0] SecondaryFactor ; | ||
+ | reg [4:0] TriggerBox ; | ||
+ | reg [7:0] ADCGate ; | ||
+ | reg [7:0] QDCGate ; | ||
+ | reg [7:0] TDCStart ; | ||
+ | reg [7:0] Coincidence ; | ||
+ | reg [4:0] Inspect1 ; | ||
+ | reg [4:0] Inspect2 ; | ||
+ | reg [4:0] Inspect3 ; | ||
+ | reg [4:0] Inspect4 ; | ||
+ | | ||
+ | // add your code here | ||
+ | always @(posedge Clock) begin | ||
+ | if (N) begin | ||
+ | case (F) | ||
+ | 5'd0: begin | ||
+ | case (A) | ||
+ | 4'd0: Data_out <= {16' | ||
+ | 4'd1: Data_out <= {16' | ||
+ | 4'd2: Data_out <= {16' | ||
+ | 4'd3: Data_out <= {16' | ||
+ | 4'd4: Data_out <= {16' | ||
+ | 4'd5: Data_out <= {16' | ||
+ | 4'd6: Data_out <= {16' | ||
+ | 4'd7: Data_out <= {19' | ||
+ | 4'd8: Data_out <= {14' | ||
+ | 4'd9: Data_out <= {14' | ||
+ | 4'd10: Data_out <= {19' | ||
+ | 4'd11: Data_out <= {23' | ||
+ | 4'd12: Data_out <= {22' | ||
+ | 4'd13: Data_out <= {23' | ||
+ | 4'd14: Data_out <= 24' | ||
+ | 4'd15: Data_out <= 24' | ||
+ | default: Data_out <= 24'd0; | ||
+ | endcase //A | ||
+ | end // F=0 | ||
+ | | ||
+ | 5'd1: begin | ||
+ | case (A) | ||
+ | 4'd0: Data_out <= {19' | ||
+ | 4'd1: Data_out <= {19' | ||
+ | 4'd2: Data_out <= {19' | ||
+ | 4'd3: Data_out <= {19' | ||
+ | default: Data_out <= 24'd0; | ||
+ | endcase //A | ||
+ | end // F=1 | ||
+ | | ||
+ | 5'd2: begin | ||
+ | case (A) | ||
+ | 4'd0: Data_out <= {16' | ||
+ | 4'd1: Data_out <= {16' | ||
+ | 4'd2: Data_out <= {16' | ||
+ | 4'd3: Data_out <= {16' | ||
+ | default: Data_out <= 24'd0; | ||
+ | endcase //A | ||
+ | end // F=2 | ||
+ | | ||
+ | 5'd3: begin | ||
+ | case (A) | ||
+ | 4'd0: Data_out <= {19' | ||
+ | 4'd1: Data_out <= {8'd0, TimeStamp[15: | ||
+ | 4'd2: Data_out <= {8'd0, TimeStamp[31: | ||
+ | 4'd3: Data_out <= {8'd0, TimeStamp[47: | ||
+ | 4'd4: Data_out <= {8'd0, TimeStamp[63: | ||
+ | default: Data_out <= 24'd0; | ||
+ | endcase //A | ||
+ | end // F=3 | ||
+ | | ||
+ | 5'd9: begin | ||
+ | end // F=9 | ||
+ | | ||
+ | 5'd16: begin | ||
+ | if (S1) begin | ||
+ | case (A) | ||
+ | 4'd0: S800Delay <= Data_in[7: | ||
+ | 4'd1: S800Width <= Data_in[7: | ||
+ | 4'd2: SecondaryDelay <= Data_in[7: | ||
+ | 4'd3: SecondaryWidth <= Data_in[7: | ||
+ | 4'd4: S800TimingDelay <= Data_in[7: | ||
+ | 4'd5: CoincTimingWidth <= Data_in[7: | ||
+ | 4'd6: SecondaryTimingDelay <= Data_in[7: | ||
+ | 4'd7: Bypasses <= Data_in[4: | ||
+ | 4'd8: S800Factor <= Data_in[9: | ||
+ | 4'd9: SecondaryFactor <= Data_in[9: | ||
+ | 4'd10: TriggerBox <= Data_in[4: | ||
+ | 4'd11: Go <= Data_in[0: | ||
+ | 4'd12: Select <= Data_in[1: | ||
+ | 4'd13: SyncEnable <= Data_in[0: | ||
+ | endcase //A | ||
+ | end // S1=1 | ||
+ | end // F=16 | ||
+ | | ||
+ | 5'd17: begin | ||
+ | if (S1) begin | ||
+ | case (A) | ||
+ | 4'd0: Inspect1 <= Data_in[4: | ||
+ | 4'd1: Inspect2 <= Data_in[4: | ||
+ | 4'd2: Inspect3 <= Data_in[4: | ||
+ | 4'd3: Inspect4 <= Data_in[4: | ||
+ | endcase //A | ||
+ | end // S1=1 | ||
+ | end // F=17 | ||
+ | | ||
+ | 5'd18: begin | ||
+ | if (S1) begin | ||
+ | case (A) | ||
+ | 4'd0: ADCGate <= Data_in[7: | ||
+ | 4'd1: QDCGate <= Data_in[7: | ||
+ | 4'd2: TDCStart <= Data_in[7: | ||
+ | 4'd3: Coincidence <= Data_in[7: | ||
+ | endcase //A | ||
+ | end // S1=1 | ||
+ | end // F=18 | ||
+ | |||
+ | endcase // F | ||
+ | end //N=1 | ||
+ | | ||
+ | end // always Clock | ||
+ | | ||
+ | always @(N or S1 or F or A) begin | ||
+ | if (N) begin | ||
+ | | ||
+ | case (F) | ||
+ | | ||
+ | 5'd0: begin | ||
+ | X = 1'b1; | ||
+ | Q = 1'b1; | ||
+ | DriveRead = 1'b1; | ||
+ | ClearModule = 1'b0; | ||
+ | ClearRegister = 1'b0; | ||
+ | end // F=0 | ||
+ | | ||
+ | 5'd1: begin | ||
+ | X = 1'b1; | ||
+ | Q = 1'b1; | ||
+ | DriveRead = 1'b1; | ||
+ | ClearModule = 1'b0; | ||
+ | ClearRegister = 1'b0; | ||
+ | end // F=1 | ||
+ | | ||
+ | 5'd2: begin | ||
+ | X = 1'b1; | ||
+ | Q = 1'b1; | ||
+ | DriveRead = 1'b1; | ||
+ | ClearModule = 1'b0; | ||
+ | ClearRegister = 1'b0; | ||
+ | end // F=2 | ||
+ | | ||
+ | 5'd3: begin | ||
+ | X = 1'b1; | ||
+ | Q = 1'b1; | ||
+ | DriveRead = 1'b1; | ||
+ | ClearModule = 1'b0; | ||
+ | ClearRegister = 1'b0; | ||
+ | end // F=3 | ||
+ | | ||
+ | 5'd9: begin | ||
+ | X = 1'b1; | ||
+ | Q = 1'b1; | ||
+ | DriveRead = 1'b0; | ||
+ | ClearModule = 1'b1; | ||
+ | ClearRegister = 1'b0; | ||
+ | end // F=9 | ||
+ | | ||
+ | 5'd10: begin | ||
+ | X = 1'b1; | ||
+ | Q = 1'b1; | ||
+ | DriveRead = 1'b0; | ||
+ | ClearModule = 1'b0; | ||
+ | ClearRegister = 1'b1; | ||
+ | end // F=9 | ||
+ | | ||
+ | 5'd16: begin | ||
+ | X = 1'b1; | ||
+ | Q = 1'b1; | ||
+ | DriveRead = 1'b0; | ||
+ | ClearModule = 1'b0; | ||
+ | ClearRegister = 1'b0; | ||
+ | end // F=16 | ||
+ | | ||
+ | 5'd17: begin | ||
+ | X = 1'b1; | ||
+ | Q = 1'b1; | ||
+ | DriveRead = 1'b0; | ||
+ | ClearModule = 1'b0; | ||
+ | ClearRegister = 1'b0; | ||
+ | end // F=17 | ||
+ | | ||
+ | 5'd18: begin | ||
+ | X = 1'b1; | ||
+ | Q = 1'b1; | ||
+ | DriveRead = 1'b0; | ||
+ | ClearModule = 1'b0; | ||
+ | ClearRegister = 1'b0; | ||
+ | end // F=18 | ||
+ | | ||
+ | default: begin | ||
+ | DriveRead = 1' | ||
+ | ClearModule = 1'b0; | ||
+ | ClearRegister = 1'b0; | ||
+ | X = 1'b0; | ||
+ | Q = 1'b0; | ||
+ | end // default F | ||
+ | | ||
+ | endcase // F | ||
+ | end // if (N) | ||
+ | | ||
+ | else begin | ||
+ | DriveRead = 1'b0; | ||
+ | ClearModule = 1'b0; | ||
+ | ClearRegister = 1'b0; | ||
+ | X = 1'b0; | ||
+ | Q = 1'b0; | ||
+ | end // if (!N) | ||
+ | end // always N or S1 or A or F | ||
+ | | ||
+ | endmodule | ||
==== CAMAC commands ==== | ==== CAMAC commands ==== | ||
Line 55: | Line 543: | ||
The following table lists the CAMAC codes recognized by the trigger module and their signification. | The following table lists the CAMAC codes recognized by the trigger module and their signification. | ||
- | F A Direction | + | |
- | 0 0 Read 16 0 Write S800 Gate & Delay (delay) | + | {|class=" |
- | 0 1 Read 16 1 Write S800 Gate & Delay (width) | + | | F |
- | 0 2 Read 16 2 Write Secondary Gate & Delay (delay) | + | | A |
- | 0 3 Read 16 3 Write Secondary Gate & Delay (width) | + | | Direction |
- | 0 4 Read 16 4 Write S800 Delay (delay) | + | | F |
- | 0 5 Read 16 5 Write Coincidence Gate (width) | + | | A |
- | 0 6 Read 16 6 Write Secondary Delay (delay) | + | | Direction |
- | 0 7 Read 16 7 Write Bypasses (bit pattern) | + | | Data |
- | 0 8 Read 16 8 Write S800 Downscaler (factor) | + | |- |
- | 0 9 Read 16 9 Write Secondary Downscaler (factor) | + | | 0 |
- | 0 10 Read 16 10 Write Trigger Box (bit pattern) | + | | 0 |
- | 0 11 Read 16 11 Write Go signal (bit) | + | | Read |
- | 0 12 Read 16 12 Write External Time Stamp Clock (bit 0) | + | | 16 |
- | and External Time Stamp Latch (bit 1) | + | | 0 |
- | + | | Write | |
- | 0 14 Read | + | | S800 Gate & Delay (delay) |
- | 0 15 Read | + | |- |
- | 1 0 Read 17 0 Write Inspect Channel 1 (wire) | + | | 0 |
- | 1 1 Read 17 1 Write Inspect Channel 2 (wire) | + | | 1 |
- | 1 2 Read 17 2 Write Inspect Channel 3 (wire) | + | | Read |
- | 1 3 Read 17 3 Write Inspect Channel 4 (wire) | + | | 16 |
- | 2 0 Read 18 0 Write ADC Gate (width) | + | | 1 |
- | 2 1 Read 18 1 Write QDC Gate (width) | + | | Write |
- | 2 2 Read 18 2 Write TDC Gate (width) | + | | S800 Gate & Delay (width) |
- | 2 3 Read 18 3 Write Coincidence Register Gate (width) | + | |- |
- | 3 0 Read | + | | 0 |
- | 3 1 Read | + | | 2 |
- | 3 2 Read | + | | Read |
- | 3 3 Read | + | | 16 |
- | 3 4 Read | + | | 2 |
+ | | Write | ||
+ | | Secondary Gate & Delay (delay) | ||
+ | |- | ||
+ | | 0 | ||
+ | | 3 | ||
+ | | Read | ||
+ | | 16 | ||
+ | | 3 | ||
+ | | Write | ||
+ | | Secondary Gate & Delay (width) | ||
+ | |- | ||
+ | | 0 | ||
+ | | 4 | ||
+ | | Read | ||
+ | | 16 | ||
+ | | 4 | ||
+ | | Write | ||
+ | | S800 Delay (delay) | ||
+ | |- | ||
+ | | 0 | ||
+ | | 5 | ||
+ | | Read | ||
+ | | 16 | ||
+ | | 5 | ||
+ | | Write | ||
+ | | Coincidence Gate (width) | ||
+ | |- | ||
+ | | 0 | ||
+ | | 6 | ||
+ | | Read | ||
+ | | 16 | ||
+ | | 6 | ||
+ | | Write | ||
+ | | Secondary Delay (delay) | ||
+ | |- | ||
+ | | 0 | ||
+ | | 7 | ||
+ | | Read | ||
+ | | 16 | ||
+ | | 7 | ||
+ | | Write | ||
+ | | Bypasses (bit pattern) | ||
+ | |- | ||
+ | | 0 | ||
+ | | 8 | ||
+ | | Read | ||
+ | | 16 | ||
+ | | 8 | ||
+ | | Write | ||
+ | | S800 Downscaler (factor) | ||
+ | |- | ||
+ | | 0 | ||
+ | | 9 | ||
+ | | Read | ||
+ | | 16 | ||
+ | | 9 | ||
+ | | Write | ||
+ | | Secondary Downscaler (factor) | ||
+ | |- | ||
+ | | 0 | ||
+ | | 10 | ||
+ | | Read | ||
+ | | 16 | ||
+ | | 10 | ||
+ | | Write | ||
+ | | Trigger Box (bit pattern) | ||
+ | |- | ||
+ | | 0 | ||
+ | | 11 | ||
+ | | Read | ||
+ | | 16 | ||
+ | | 11 | ||
+ | | Write | ||
+ | | Go signal (bit) | ||
+ | |- | ||
+ | | 0 | ||
+ | | 12 | ||
+ | | Read | ||
+ | | 16 | ||
+ | | 12 | ||
+ | | Write | ||
+ | | External Time Stamp Clock (bit 0) | ||
+ | and External Time Stamp Latch (bit 1) | ||
+ | |- | ||
+ | | 0 | ||
+ | | 14 | ||
+ | | Read | ||
+ | | | ||
+ | | | ||
+ | | | ||
+ | | Signature 1 (0x5800) | ||
+ | |- | ||
+ | | 0 | ||
+ | | 15 | ||
+ | | Read | ||
+ | | | ||
+ | | | ||
+ | | | ||
+ | | Signature 2 (0x2367) | ||
+ | |- | ||
+ | | 1 | ||
+ | | 0 | ||
+ | | Read | ||
+ | | 17 | ||
+ | | 0 | ||
+ | | Write | ||
+ | | Inspect Channel 1 (wire) | ||
+ | |- | ||
+ | | 1 | ||
+ | | 1 | ||
+ | | Read | ||
+ | | 17 | ||
+ | | 1 | ||
+ | | Write | ||
+ | | Inspect Channel 2 (wire) | ||
+ | |- | ||
+ | | 1 | ||
+ | | 2 | ||
+ | | Read | ||
+ | | 17 | ||
+ | | 2 | ||
+ | | Write | ||
+ | | Inspect Channel 3 (wire) | ||
+ | |- | ||
+ | | 1 | ||
+ | | 3 | ||
+ | | Read | ||
+ | | 17 | ||
+ | | 3 | ||
+ | | Write | ||
+ | | Inspect Channel 4 (wire) | ||
+ | |- | ||
+ | | 2 | ||
+ | | 0 | ||
+ | | Read | ||
+ | | 18 | ||
+ | | 0 | ||
+ | | Write | ||
+ | | ADC Gate (width) | ||
+ | |- | ||
+ | | 2 | ||
+ | | 1 | ||
+ | | Read | ||
+ | | 18 | ||
+ | | 1 | ||
+ | | Write | ||
+ | | QDC Gate (width) | ||
+ | |- | ||
+ | | 2 | ||
+ | | 2 | ||
+ | | Read | ||
+ | | 18 | ||
+ | | 2 | ||
+ | | Write | ||
+ | | TDC Gate (width) | ||
+ | |- | ||
+ | | 2 | ||
+ | | 3 | ||
+ | | Read | ||
+ | | 18 | ||
+ | | 3 | ||
+ | | Write | ||
+ | | Coincidence Register Gate (width) | ||
+ | |- | ||
+ | | 3 | ||
+ | | 0 | ||
+ | | Read | ||
+ | | | ||
+ | | | ||
+ | | | ||
+ | | Trigger Box Register (bit pattern) | ||
+ | |- | ||
+ | | 3 | ||
+ | | 1 | ||
+ | | Read | ||
+ | | | ||
+ | | | ||
+ | | | ||
+ | | Time Stamp (bits 0-15) | ||
+ | |- | ||
+ | | 3 | ||
+ | | 2 | ||
+ | | Read | ||
+ | | | ||
+ | | | ||
+ | | | ||
+ | | Time Stamp (bits 16-31) | ||
+ | |- | ||
+ | | 3 | ||
+ | | 3 | ||
+ | | Read | ||
+ | | | ||
+ | | | ||
+ | | | ||
+ | | Time Stamp (bits 32-47) | ||
+ | |- | ||
+ | | 3 | ||
+ | | 4 | ||
+ | | Read | ||
+ | | | ||
+ | | | ||
+ | | | ||
+ | | Time Stamp (bits 48-63) | ||
+ | |} | ||