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trigger [2013/12/11 14:48]
pereira [CAMAC commands] 		trigger [2013/12/11 14:57]
pereira [CAMAC commands]
Line 55: Line 55:
 The following table lists the CAMAC codes recognized by the trigger module and their signification. The following table lists the CAMAC codes recognized by the trigger module and their signification.
  
-{|class="wikitable" + 
-| F +^ F ^ A ^ Direction ^ F ^ A ^ Direction ^ Data | 
-| A +| 0 | 0 | Read | 16 | 0 | Write | S800 Gate & Delay (delay) |
-| Direction +
-| F +
-| A +
-| Direction +
-| Data +
-|- +
-| 0 +
-| 0 +
-| Read +
-| 16 +
-| 0 +
-| Write +
-| S800 Gate & Delay (delay) +
-|-+
 | 0 | 0
 | 1 | 1
Line 747: Line 733:
 The following table lists the CAMAC codes recognized by the trigger module and their signification.  The following table lists the CAMAC codes recognized by the trigger module and their signification. 
  
-F  A  Direction  F  A  Direction  Data   + 
-0  0  Read  16  0  Write  S800 Gate & Delay (delay)   +{|class="wikitable" 
-0  1  Read  16  1  Write  S800 Gate & Delay (width)   +| F 
-0  2  Read  16  2  Write  Secondary Gate & Delay (delay)   +| A 
-0  3  Read  16  3  Write  Secondary Gate & Delay (width)   +| Direction 
-0  4  Read  16  4  Write  S800 Delay (delay)   +| F 
-0  5  Read  16  5  Write  Coincidence Gate (width)   +| A 
-0  6  Read  16  6  Write  Secondary Delay (delay)   +| Direction 
-0  7  Read  16  7  Write  Bypasses (bit pattern)   +| Data 
-0  8  Read  16  8  Write  S800 Downscaler (factor)   +|- 
-0  9  Read  16  9  Write  Secondary Downscaler (factor)   +| 0 
-0  10  Read  16  10  Write  Trigger Box (bit pattern)   +| 0 
-0  11  Read  16  11  Write  Go signal (bit)   +| Read 
-0  12  Read  16  12  Write  External Time Stamp Clock (bit 0)  +| 16 
-and External Time Stamp Latch (bit 1)  +| 0 
-  +| Write 
-0  14  Read     Signature 1 (0x5800)   +| S800 Gate & Delay (delay) 
-0  15  Read     Signature 2 (0x2367)   +|- 
-1  0  Read  17  0  Write  Inspect Channel 1 (wire)   +| 0 
-1  1  Read  17  1  Write  Inspect Channel 2 (wire)   +| 1 
-1  2  Read  17  2  Write  Inspect Channel 3 (wire)   +| Read 
-1  3  Read  17  3  Write  Inspect Channel 4 (wire)   +| 16 
-2  0  Read  18  0  Write  ADC Gate (width)   +| 1 
-2  1  Read  18  1  Write  QDC Gate (width)   +| Write 
-2  2  Read  18  2  Write  TDC Gate (width)   +| S800 Gate & Delay (width) 
-2  3  Read  18  3  Write  Coincidence Register Gate (width)   +|- 
-3  0  Read     Trigger Box Register (bit pattern)   +| 0 
-3  1  Read     Time Stamp (bits 0-15)   +| 2 
-3  2  Read     Time Stamp (bits 16-31)   +| Read 
-3  3  Read     Time Stamp (bits 32-47)   +| 16 
-3  4  Read     Time Stamp (bits 48-63)  +| 2 
 +| Write 
 +| Secondary Gate & Delay (delay) 
 +|- 
 +| 0 
 +| 3 
 +| Read 
 +| 16 
 +| 3 
 +| Write 
 +| Secondary Gate & Delay (width) 
 +|- 
 +| 0 
 +| 4 
 +| Read 
 +| 16 
 +| 4 
 +| Write 
 +| S800 Delay (delay) 
 +|- 
 +| 0 
 +| 5 
 +| Read 
 +| 16 
 +| 5 
 +| Write 
 +| Coincidence Gate (width) 
 +|- 
 +| 0 
 +| 6 
 +| Read 
 +| 16 
 +| 6 
 +| Write 
 +| Secondary Delay (delay) 
 +|- 
 +| 0 
 +| 7 
 +| Read 
 +| 16 
 +| 7 
 +| Write 
 +| Bypasses (bit pattern) 
 +|- 
 +| 0 
 +| 8 
 +| Read 
 +| 16 
 +| 8 
 +| Write 
 +| S800 Downscaler (factor) 
 +|- 
 +| 0 
 +| 9 
 +| Read 
 +| 16 
 +| 9 
 +| Write 
 +| Secondary Downscaler (factor) 
 +|- 
 +| 0 
 +| 10 
 +| Read 
 +| 16 
 +| 10 
 +| Write 
 +| Trigger Box (bit pattern) 
 +|- 
 +| 0 
 +| 11 
 +| Read 
 +| 16 
 +| 11 
 +| Write 
 +| Go signal (bit) 
 +|- 
 +| 0 
 +| 12 
 +| Read 
 +| 16 
 +| 12 
 +| Write 
 +| External Time Stamp Clock (bit 0) 
 +and External Time Stamp Latch (bit 1) 
 +|- 
 +| 0 
 +| 14 
 +| Read 
 +|  
 +|  
 +| 
 +| Signature 1 (0x5800) 
 +|- 
 +| 0 
 +| 15 
 +| Read 
 +|  
 +|  
 +| 
 +| Signature 2 (0x2367) 
 +|- 
 +| 1 
 +| 0 
 +| Read 
 +| 17 
 +| 0 
 +| Write 
 +| Inspect Channel 1 (wire) 
 +|- 
 +| 1 
 +| 1 
 +| Read 
 +| 17 
 +| 1 
 +| Write 
 +| Inspect Channel 2 (wire) 
 +|- 
 +| 1 
 +| 2 
 +| Read 
 +| 17 
 +| 2 
 +| Write 
 +| Inspect Channel 3 (wire) 
 +|- 
 +| 1 
 +| 3 
 +| Read 
 +| 17 
 +| 3 
 +| Write 
 +| Inspect Channel 4 (wire) 
 +|- 
 +| 2 
 +| 0 
 +| Read 
 +| 18 
 +| 0 
 +| Write 
 +| ADC Gate (width) 
 +|- 
 +| 2 
 +| 1 
 +| Read 
 +| 18 
 +| 1 
 +| Write 
 +| QDC Gate (width) 
 +|- 
 +| 2 
 +| 2 
 +| Read 
 +| 18 
 +| 2 
 +| Write 
 +| TDC Gate (width) 
 +|- 
 +| 2 
 +| 3 
 +| Read 
 +| 18 
 +| 3 
 +| Write 
 +| Coincidence Register Gate (width) 
 +|- 
 +| 3 
 +| 0 
 +| Read 
 +| 
 +| 
 +| 
 +| Trigger Box Register (bit pattern) 
 +|- 
 +| 3 
 +| 1 
 +| Read 
 +| 
 +| 
 +| 
 +| Time Stamp (bits 0-15) 
 +|- 
 +| 3 
 +| 2 
 +| Read 
 +| 
 +| 
 +| 
 +| Time Stamp (bits 16-31) 
 +|- 
 +| 3 
 +| 3 
 +| Read 
 +| 
 +| 
 +| 
 +| Time Stamp (bits 32-47) 
 +|- 
 +| 3 
 +| 4 
 +| Read 
 +| 
 +| 
 +| 
 +| Time Stamp (bits 48-63) 
 +|}
  
  
trigger.txt · Last modified: 2023/10/24 16:47 by swartzj

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