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trigger [2013/12/11 15:20] pereira [CAMAC commands] |
trigger [2013/12/11 15:42] pereira [Inputs and outputs] |
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==== CAMAC commands ==== | ==== CAMAC commands ==== | ||
- | The table with a lists of the CAMAC commands recognized by the trigger module and their signification can be found [[CAMAC commands | here]]. | + | A table with the list of the CAMAC commands recognized by the trigger module and their signification can be found [[CAMAC commands | here]]. |
- | ==Inputs and outputs== | + | ==== Inputs and outputs |
- | The following | + | A table with the list of inputs/outputs |
- | + | ||
- | {| class=" | + | |
- | | Pin | + | |
- | | Assignment | + | |
- | | Pin | + | |
- | | Assignment | + | |
- | | Pin | + | |
- | | Assignment | + | |
- | | Pin | + | |
- | | Assignment | + | |
- | |- | + | |
- | | A1 (in) | + | |
- | | S800 source | + | |
- | | B1 (out) | + | |
- | | Raw trigger | + | |
- | | C1 (in) | + | |
- | | Busy 1 | + | |
- | | D1 (out) | + | |
- | | S800 source | + | |
- | |- | + | |
- | | A2 (in) | + | |
- | | Secondary source | + | |
- | | B2 (out) | + | |
- | | Live trigger | + | |
- | | C2 (in) | + | |
- | | Busy 2 | + | |
- | | D2 (out) | + | |
- | | Secondary source | + | |
- | |- | + | |
- | | A3 (in) | + | |
- | | External 1 source | + | |
- | | B3 (out) | + | |
- | | ADC gate | + | |
- | | C3 (in) | + | |
- | | Busy 3 | + | |
- | | D3 (out) | + | |
- | | External 1 source | + | |
- | |- | + | |
- | | A4 (in) | + | |
- | | External 2 source | + | |
- | | B4 (out) | + | |
- | | QDC gate | + | |
- | | C4 (in) | + | |
- | | Busy 4 | + | |
- | | D4 (out) | + | |
- | | External 2 source | + | |
- | |- | + | |
- | | A5 (in) | + | |
- | | Clear busy | + | |
- | | B5 (out) | + | |
- | | TDC start | + | |
- | | C5 (in) | + | |
- | | Busy 5 | + | |
- | | D5 (out) | + | |
- | | S800 trigger | + | |
- | |- | + | |
- | | A6 (in) | + | |
- | | Clear module | + | |
- | | B6 (out) | + | |
- | | Trigger register gate | + | |
- | | C6 (in) | + | |
- | | Busy 6 | + | |
- | | D6 (out) | + | |
- | | Coincidence trigger | + | |
- | |- | + | |
- | | A7 (in) | + | |
- | | Gretina sync | + | |
- | | B7 (out) | + | |
- | | | + | |
- | | C7 (in) | + | |
- | | Busy 7 | + | |
- | | D7 (out) | + | |
- | | External 1 trigger | + | |
- | |- | + | |
- | | A8 (in) | + | |
- | | Time stamp clock | + | |
- | | B8 (out) | + | |
- | | Live trigger | + | |
- | | C8 (in) | + | |
- | | Time stamp latch | + | |
- | | D8 (out) | + | |
- | | External 2 trigger | + | |
- | |- | + | |
- | | | + | |
- | | | + | |
- | | B9 (out) | + | |
- | | Inspect 1 | + | |
- | | C9 (out) | + | |
- | | Time stamp clock | + | |
- | | D9 (out) | + | |
- | | Secondary trigger | + | |
- | |- | + | |
- | | | + | |
- | | | + | |
- | | B10 (out) | + | |
- | | Inspect 2 | + | |
- | | C10 (out) | + | |
- | | Time stamp latch | + | |
- | | D10 (out) | + | |
- | | Raw trigger | + | |
- | |- | + | |
- | | | + | |
- | | | + | |
- | | B11 (out) | + | |
- | | Inspect 3 | + | |
- | | C11 (out) | + | |
- | | | + | |
- | | D11 (out) | + | |
- | | Live trigger | + | |
- | |- | + | |
- | | | + | |
- | | | + | |
- | | B12 (out) | + | |
- | | Inspect 4 | + | |
- | | C12 (out) | + | |
- | | | + | |
- | | D12 (out) | + | |
- | | Raw pulser | + | |
- | |- | + | |
- | | | + | |
- | | | + | |
- | | B13 (out) | + | |
- | | Fast clear | + | |
- | | C13 (out) | + | |
- | | | + | |
- | | D13 (out) | + | |
- | | Live pulser | + | |
- | |- | + | |
- | | | + | |
- | | | + | |
- | | B14 (out) | + | |
- | | | + | |
- | | C14 (out) | + | |
- | | | + | |
- | | D14 (out) | + | |
- | | Fast clear | + | |
- | |- | + | |
- | | | + | |
- | | | + | |
- | | B15 (out) | + | |
- | | Go | + | |
- | | C15 (out) | + | |
- | | | + | |
- | | D15 (out) | + | |
- | | 10 Hz | + | |
- | |- | + | |
- | | | + | |
- | | | + | |
- | | B16 (out) | + | |
- | | Time stamp clock | + | |
- | | C16 (out) | + | |
- | | | + | |
- | | D16 (out) | + | |
- | | 1 Hz | + | |
- | |} | + | |
- | ==FPGA firmware== | + | ==== FPGA firmware |
- | The firmware of the trigger module is shown in the following files. The PDF file contains the schematic sheets, used for most of the design. The Verilog file contains the block dealing with CAMAC communications. | + | The firmware of the trigger module is shown in the following files. The [[ |PDF file]] contains the schematic sheets, used for most of the design. The Verilog file contains the block dealing with CAMAC communications. |
File containing the schematics: [[File: | File containing the schematics: [[File: | ||
Line 514: | Line 359: | ||
- | |||
- | |||
- | ^ F ^ A ^ Direction ^ F ^ A ^ Direction ^ Data ^ | ||
- | | 0 | 0 | Read | 16 | 0 | Write | S800 Gate & Delay (delay) | | ||
- | | 0 | 1 | Read | 16 | 1 | Write | S800 Gate & Delay (width) | | ||
- | | 0 | 2 | Read | 16 | 2 | Write | Secondary Gate & Delay (delay) | | ||
- | | 0 | 3 | Read | 16 | 3 | Write | Secondary Gate & Delay (width) | | ||
- | | 0 | 4 | Read | 16 | 4 | Write | S800 Delay (delay) | | ||
- | | 0 | 5 | Read | 16 | 5 | Write | Coincidence Gate (width) | | ||
- | | 0 | 6 | Read | 16 | 6 | Write | Secondary Delay (delay) | | ||
- | | 0 | 7 | Read | 16 | 7 | Write | Bypasses (bit pattern) | | ||
- | | 0 | 8 | Read | 16 | 8 | Write | S800 Downscaler (factor) | | ||
- | | 0 | 9 | Read | 16 | 9 | Write | Secondary Downscaler (factor) | | ||
- | | 0 | 10 | Read | 16 | 10 | Write | Trigger Box (bit pattern) | | ||
- | | 0 | 11 | Read | 16 | 11 | Write | Go signal (bit) | | ||
- | | 0 | 12 | Read | 16 | 12 | Write | External Time Stamp Clock (bit 0)and External Time Stamp Latch (bit 1) | | ||
- | | 0 | 14 | Read | | | | Signature 1 (0x5800) | | ||
- | | 0 | 15 | Read | | | | Signature 2 (0x2367) | | ||
- | | 1 | 0 | Read | 17 | 0 | Write | Inspect Channel 1 (wire) | | ||
- | | 1 | 1 | Read | 17 | 1 | Write | Inspect Channel 2 (wire) | | ||
- | | 1 | 2 | Read | 17 | 2 | Write | Inspect Channel 3 (wire) | | ||
- | | 1 | 3 | Read | 17 | 3 | Write | Inspect Channel 4 (wire) | | ||
- | | 2 | 0 | Read | 18 | 0 | Write | ADC Gate (width) | | ||
- | | 2 | 1 | Read | 18 | 1 | Write | QDC Gate (width) | | ||
- | | 2 | 2 | Read | 18 | 2 | Write | TDC Gate (width) | | ||
- | | 2 | 3 | Read | 18 | 3 | Write | Coincidence Register Gate (width) | | ||
- | | 3 | 0 | Read | | | | Trigger Box Register (bit pattern) | | ||
- | | 3 | 1 | Read | | | | Time Stamp (bits 0-15) | | ||
- | | 3 | 2 | Read | | | | Time Stamp (bits 16-31) | | ||
- | | 3 | 3 | Read | | | | Time Stamp (bits 32-47) | | ||
- | | 3 | 4 | Read | | | | Time Stamp (bits 48-63) | | ||
- | |||
- | |||
- | ==== CAMAC commands ==== | ||
- | |||
- | The following table lists the CAMAC codes recognized by the trigger module and their signification. | ||
- | |||
- | |||
- | {|class=" | ||
- | | F | ||
- | | A | ||
- | | Direction | ||
- | | F | ||
- | | A | ||
- | | Direction | ||
- | | Data | ||
- | |- | ||
- | | 0 | ||
- | | 0 | ||
- | | Read | ||
- | | 16 | ||
- | | 0 | ||
- | | Write | ||
- | | S800 Gate & Delay (delay) | ||
- | |- | ||
- | | 0 | ||
- | | 1 | ||
- | | Read | ||
- | | 16 | ||
- | | 1 | ||
- | | Write | ||
- | | S800 Gate & Delay (width) | ||
- | |- | ||
- | | 0 | ||
- | | 2 | ||
- | | Read | ||
- | | 16 | ||
- | | 2 | ||
- | | Write | ||
- | | Secondary Gate & Delay (delay) | ||
- | |- | ||
- | | 0 | ||
- | | 3 | ||
- | | Read | ||
- | | 16 | ||
- | | 3 | ||
- | | Write | ||
- | | Secondary Gate & Delay (width) | ||
- | |- | ||
- | | 0 | ||
- | | 4 | ||
- | | Read | ||
- | | 16 | ||
- | | 4 | ||
- | | Write | ||
- | | S800 Delay (delay) | ||
- | |- | ||
- | | 0 | ||
- | | 5 | ||
- | | Read | ||
- | | 16 | ||
- | | 5 | ||
- | | Write | ||
- | | Coincidence Gate (width) | ||
- | |- | ||
- | | 0 | ||
- | | 6 | ||
- | | Read | ||
- | | 16 | ||
- | | 6 | ||
- | | Write | ||
- | | Secondary Delay (delay) | ||
- | |- | ||
- | | 0 | ||
- | | 7 | ||
- | | Read | ||
- | | 16 | ||
- | | 7 | ||
- | | Write | ||
- | | Bypasses (bit pattern) | ||
- | |- | ||
- | | 0 | ||
- | | 8 | ||
- | | Read | ||
- | | 16 | ||
- | | 8 | ||
- | | Write | ||
- | | S800 Downscaler (factor) | ||
- | |- | ||
- | | 0 | ||
- | | 9 | ||
- | | Read | ||
- | | 16 | ||
- | | 9 | ||
- | | Write | ||
- | | Secondary Downscaler (factor) | ||
- | |- | ||
- | | 0 | ||
- | | 10 | ||
- | | Read | ||
- | | 16 | ||
- | | 10 | ||
- | | Write | ||
- | | Trigger Box (bit pattern) | ||
- | |- | ||
- | | 0 | ||
- | | 11 | ||
- | | Read | ||
- | | 16 | ||
- | | 11 | ||
- | | Write | ||
- | | Go signal (bit) | ||
- | |- | ||
- | | 0 | ||
- | | 12 | ||
- | | Read | ||
- | | 16 | ||
- | | 12 | ||
- | | Write | ||
- | | External Time Stamp Clock (bit 0) | ||
- | and External Time Stamp Latch (bit 1) | ||
- | |- | ||
- | | 0 | ||
- | | 14 | ||
- | | Read | ||
- | | | ||
- | | | ||
- | | | ||
- | | Signature 1 (0x5800) | ||
- | |- | ||
- | | 0 | ||
- | | 15 | ||
- | | Read | ||
- | | | ||
- | | | ||
- | | | ||
- | | Signature 2 (0x2367) | ||
- | |- | ||
- | | 1 | ||
- | | 0 | ||
- | | Read | ||
- | | 17 | ||
- | | 0 | ||
- | | Write | ||
- | | Inspect Channel 1 (wire) | ||
- | |- | ||
- | | 1 | ||
- | | 1 | ||
- | | Read | ||
- | | 17 | ||
- | | 1 | ||
- | | Write | ||
- | | Inspect Channel 2 (wire) | ||
- | |- | ||
- | | 1 | ||
- | | 2 | ||
- | | Read | ||
- | | 17 | ||
- | | 2 | ||
- | | Write | ||
- | | Inspect Channel 3 (wire) | ||
- | |- | ||
- | | 1 | ||
- | | 3 | ||
- | | Read | ||
- | | 17 | ||
- | | 3 | ||
- | | Write | ||
- | | Inspect Channel 4 (wire) | ||
- | |- | ||
- | | 2 | ||
- | | 0 | ||
- | | Read | ||
- | | 18 | ||
- | | 0 | ||
- | | Write | ||
- | | ADC Gate (width) | ||
- | |- | ||
- | | 2 | ||
- | | 1 | ||
- | | Read | ||
- | | 18 | ||
- | | 1 | ||
- | | Write | ||
- | | QDC Gate (width) | ||
- | |- | ||
- | | 2 | ||
- | | 2 | ||
- | | Read | ||
- | | 18 | ||
- | | 2 | ||
- | | Write | ||
- | | TDC Gate (width) | ||
- | |- | ||
- | | 2 | ||
- | | 3 | ||
- | | Read | ||
- | | 18 | ||
- | | 3 | ||
- | | Write | ||
- | | Coincidence Register Gate (width) | ||
- | |- | ||
- | | 3 | ||
- | | 0 | ||
- | | Read | ||
- | | | ||
- | | | ||
- | | | ||
- | | Trigger Box Register (bit pattern) | ||
- | |- | ||
- | | 3 | ||
- | | 1 | ||
- | | Read | ||
- | | | ||
- | | | ||
- | | | ||
- | | Time Stamp (bits 0-15) | ||
- | |- | ||
- | | 3 | ||
- | | 2 | ||
- | | Read | ||
- | | | ||
- | | | ||
- | | | ||
- | | Time Stamp (bits 16-31) | ||
- | |- | ||
- | | 3 | ||
- | | 3 | ||
- | | Read | ||
- | | | ||
- | | | ||
- | | | ||
- | | Time Stamp (bits 32-47) | ||
- | |- | ||
- | | 3 | ||
- | | 4 | ||
- | | Read | ||
- | | | ||
- | | | ||
- | | | ||
- | | Time Stamp (bits 48-63) | ||
- | |} | ||
- | |||
- | |||
- | ==== Inputs and outputs ==== | ||
- | The following table lists the inputs and outputs to/from the trigger module and their assignment. | ||
- | |||
- | Pin Assignment | ||
- | A1 (in) S800 source | ||
- | A2 (in) Secondary source | ||
- | A3 (in) External 1 source | ||
- | A4 (in) External 2 source | ||
- | A5 (in) Clear busy B5 (out) TDC start C5 (in) Busy 5 D5 (out) S800 trigger | ||
- | A6 (in) Clear module | ||
- | A7 (in) Gretina sync B7 (out) C7 (in) Busy 7 D7 (out) External 1 trigger | ||
- | A8 (in) Time stamp clock B8 (out) Live trigger | ||
- | B9 (out) Inspect 1 C9 (out) Time stamp clock D9 (out) Secondary trigger | ||
- | B10 (out) Inspect 2 C10 (out) Time stamp latch D10 (out) Raw trigger | ||
- | B11 (out) Inspect 3 C11 (out) D11 (out) Live trigger | ||
- | B12 (out) Inspect 4 C12 (out) D12 (out) Raw pulser | ||
- | B13 (out) Fast clear C13 (out) D13 (out) Live pulser | ||
- | B14 (out) C14 (out) D14 (out) Fast clear | ||
- | B15 (out) Go C15 (out) D15 (out) 10 Hz | ||
- | B16 (out) Time stamp clock C16 (out) D16 (out) 1 Hz | ||
==== FPGA firmware ==== | ==== FPGA firmware ==== |