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trigger [2013/12/11 15:20]
pereira [CAMAC commands] 		trigger [2013/12/11 16:14]
pereira [Time stamping]
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 ==== Time Stamping Scheme ==== ==== Time Stamping Scheme ====
-Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping schemes are incorporated in the trigger to synchronize events. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward. More details about the time stamping module can be found in section "[[Trigger#Time stamping|Time stamping]]".+Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping schemes are incorporated in the trigger to synchronize events. Because of this modularity, the same synchronization scheme can be used when coupling external data acquisition systems to the S800.
  
 +
 +More details about the time stamping module can be found in section "[[Trigger#Time stamping|Time stamping]]".
  
 ===== Trigger module ===== ===== Trigger module =====
-The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/outputs (such as the VME XLM72 module for instance). This section describes the functionality of the S800 trigger module and the commands used to control its parameters. +The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/outputs (such as the VME XLM72 module for instance). This section contains the functionality of the S800 trigger module and the commands used to control its parameters. 
  
 ==== CAMAC commands ==== ==== CAMAC commands ====
  
-The table with a lists of the CAMAC commands recognized by the trigger module and their signification can be found [[CAMAC commands | here]]. +A table with the list of the CAMAC commands recognized by the trigger module and their signification can be found [[CAMAC commands | here]].
- +
- +
-==Inputs and outputs== +
-The following table lists the inputs and outputs to/from the trigger module and their assignment. +
- +
-{| class="wikitable" +
-| Pin +
-| Assignment +
-| Pin +
-| Assignment +
-| Pin +
-| Assignment +
-| Pin +
-| Assignment +
-|- +
-| A1 (in) +
-| S800 source +
-| B1 (out) +
-| Raw trigger +
-| C1 (in) +
-| Busy 1 +
-| D1 (out) +
-| S800 source +
-|- +
-| A2 (in) +
-| Secondary source +
-| B2 (out) +
-| Live trigger +
-| C2 (in) +
-| Busy 2 +
-| D2 (out) +
-| Secondary source +
-|- +
-| A3 (in) +
-| External 1 source +
-| B3 (out) +
-| ADC gate +
-| C3 (in) +
-| Busy 3 +
-| D3 (out) +
-| External 1 source +
-|- +
-| A4 (in) +
-| External 2 source +
-| B4 (out) +
-| QDC gate +
-| C4 (in) +
-| Busy 4 +
-| D4 (out) +
-| External 2 source +
-|- +
-| A5 (in) +
-| Clear busy +
-| B5 (out) +
-| TDC start +
-| C5 (in) +
-| Busy 5 +
-| D5 (out) +
-| S800 trigger +
-|- +
-| A6 (in) +
-| Clear module +
-| B6 (out) +
-| Trigger register gate +
-| C6 (in) +
-| Busy 6 +
-| D6 (out) +
-| Coincidence trigger +
-|- +
-| A7 (in) +
-| Gretina sync +
-| B7 (out) +
-|  +
-| C7 (in) +
-| Busy 7 +
-| D7 (out) +
-| External 1 trigger +
-|- +
-| A8 (in) +
-| Time stamp clock +
-| B8 (out) +
-| Live trigger +
-| C8 (in) +
-| Time stamp latch +
-| D8 (out) +
-| External 2 trigger +
-|- +
-| +
-| +
-| B9 (out) +
-| Inspect 1 +
-| C9 (out) +
-| Time stamp clock +
-| D9 (out) +
-| Secondary trigger +
-|- +
-| +
-| +
-| B10 (out) +
-| Inspect 2 +
-| C10 (out) +
-| Time stamp latch +
-| D10 (out) +
-| Raw trigger +
-|- +
-| +
-| +
-| B11 (out) +
-| Inspect 3 +
-| C11 (out) +
-|  +
-| D11 (out) +
-| Live trigger +
-|- +
-| +
-| +
-| B12 (out) +
-| Inspect 4 +
-| C12 (out) +
-|  +
-| D12 (out) +
-| Raw pulser +
-|- +
-| +
-| +
-| B13 (out) +
-| Fast clear +
-| C13 (out) +
-|  +
-| D13 (out) +
-| Live pulser +
-|- +
-| +
-| +
-| B14 (out) +
-|  +
-| C14 (out) +
-|  +
-| D14 (out) +
-| Fast clear +
-|- +
-| +
-| +
-| B15 (out) +
-| Go +
-| C15 (out) +
-|  +
-| D15 (out) +
-| 10 Hz +
-|- +
-| +
-| +
-| B16 (out) +
-| Time stamp clock +
-| C16 (out) +
-|  +
-| D16 (out) +
-| 1 Hz +
-|} +
- +
-==FPGA firmware== +
-The firmware of the trigger module is shown in the following files. The PDF file contains the schematic sheets, used for most of the design. The Verilog file contains the block dealing with CAMAC communications. +
- +
-File containing the schematics: [[File:usbtrig.pdf|100px|thumb|usbtrig.pdf]] +
- +
-Below is the Verilog code used in the configuration for the INTERNAL module: +
- +
-  module INTERNAL (N, S1, S2, Clock, F, A, Data_in,  +
-  DriveRead, Q, X, Data_out,  +
-  S800Delay, S800Width,  +
-  SecondaryDelay, SecondaryWidth,  +
-  S800TimingDelay, CoincTimingWidth, +
-  SecondaryTimingDelay, Bypasses, +
-  S800Factor, SecondaryFactor, TriggerBox, +
-  ADCGate, QDCGate, TDCStart, Coincidence, +
-  Inspect1, Inspect2, Inspect3, Inspect4, +
-  Register, ClearModule, ClearRegister, Go,  +
-  TimeStamp, Select, SyncEnable +
-  ) ; +
-   +
-  input N ; +
-  input S1 ; +
-  input S2 ; +
-  input Clock ; +
-  input [4:0] F ; +
-  input [3:0] A ; +
-  input [23:0] Data_in ; +
-  output Q ; +
-  output X ; +
-  output DriveRead; +
-  output [23:0] Data_out ; +
-  output [7:0] S800Delay; +
-  output [7:0] S800Width ; +
-  output [7:0] SecondaryDelay; +
-  output [7:0] SecondaryWidth ; +
-  output [7:0] S800TimingDelay; +
-  output [7:0] CoincTimingWidth ; +
-  output [7:0] SecondaryTimingDelay ; +
-  output [4:0] Bypasses ; +
-  output [9:0] S800Factor ; +
-  output [9:0] SecondaryFactor ; +
-  output [4:0] TriggerBox ; +
-  output [7:0] ADCGate ; +
-  output [7:0] QDCGate ; +
-  output [7:0] TDCStart ; +
-  output [7:0] Coincidence ; +
-  output [4:0] Inspect1 ; +
-  output [4:0] Inspect2 ; +
-  output [4:0] Inspect3 ; +
-  output [4:0] Inspect4 ; +
-  input [4:0] Register; +
-  output ClearModule; +
-  output ClearRegister; +
-  output Go; +
-  input [63:0] TimeStamp; +
-  output [1:0] Select; +
-  output SyncEnable; +
-   +
-  // add your declarations here +
-  reg X; +
-  reg Q; +
-  reg DriveRead ; +
-  reg ClearModule; +
-  reg ClearRegister; +
-  reg Go; +
-  reg [1:0] Select; +
-  reg SyncEnable; +
-  reg [23:0] Data_out ; +
-  reg [7:0] S800Delay; +
-  reg [7:0] S800Width ; +
-  reg [7:0] SecondaryDelay; +
-  reg [7:0] SecondaryWidth ; +
-  reg [7:0] S800TimingDelay; +
-  reg [7:0] CoincTimingWidth ; +
-  reg [7:0] SecondaryTimingDelay ; +
-  reg [4:0] Bypasses ; +
-  reg [9:0] S800Factor ; +
-  reg [9:0] SecondaryFactor ; +
-  reg [4:0] TriggerBox ; +
-  reg [7:0] ADCGate ; +
-  reg [7:0] QDCGate ; +
-  reg [7:0] TDCStart ; +
-  reg [7:0] Coincidence ; +
-  reg [4:0] Inspect1 ; +
-  reg [4:0] Inspect2 ; +
-  reg [4:0] Inspect3 ; +
-  reg [4:0] Inspect4 ; +
-   +
-  // add your code here +
-  always @(posedge Clock) begin +
-    if (N) begin +
-    case (F) +
-      5'd0: begin +
-      case (A) +
-        4'd0: Data_out <= {16'd0, S800Delay}; +
-        4'd1: Data_out <= {16'd0, S800Width}; +
-        4'd2: Data_out <= {16'd0, SecondaryDelay}; +
-        4'd3: Data_out <= {16'd0, SecondaryWidth}; +
-        4'd4: Data_out <= {16'd0, S800TimingDelay}; +
-        4'd5: Data_out <= {16'd0, CoincTimingWidth}; +
-        4'd6: Data_out <= {16'd0, SecondaryTimingDelay}; +
-        4'd7: Data_out <= {19'd0, Bypasses}; +
-        4'd8: Data_out <= {14'd0, S800Factor}; +
-        4'd9: Data_out <= {14'd0, SecondaryFactor}; +
-        4'd10: Data_out <= {19'd0, TriggerBox}; +
-        4'd11: Data_out <= {23'd0, Go}; +
-        4'd12: Data_out <= {22'd0, Select}; +
-        4'd13: Data_out <= {23'd0, SyncEnable}; +
-        4'd14: Data_out <= 24'd5800; +
-        4'd15: Data_out <= 24'd2367; +
-        default: Data_out <= 24'd0; +
-      endcase //A +
-      end // F=0 +
-       +
-      5'd1: begin +
-      case (A) +
-        4'd0: Data_out <= {19'd0, Inspect1}; +
-        4'd1: Data_out <= {19'd0, Inspect2}; +
-        4'd2: Data_out <= {19'd0, Inspect3}; +
-        4'd3: Data_out <= {19'd0, Inspect4}; +
-        default: Data_out <= 24'd0; +
-      endcase //A +
-      end // F=1 +
-       +
-      5'd2: begin +
-      case (A) +
-        4'd0: Data_out <= {16'd0, ADCGate}; +
-        4'd1: Data_out <= {16'd0, QDCGate}; +
-        4'd2: Data_out <= {16'd0, TDCStart}; +
-        4'd3: Data_out <= {16'd0, Coincidence}; +
-        default: Data_out <= 24'd0; +
-      endcase //A +
-      end // F=2 +
-       +
-      5'd3: begin +
-      case (A) +
-        4'd0: Data_out <= {19'd0, Register}; +
-        4'd1: Data_out <= {8'd0, TimeStamp[15:0]}; +
-        4'd2: Data_out <= {8'd0, TimeStamp[31:16]}; +
-        4'd3: Data_out <= {8'd0, TimeStamp[47:32]}; +
-        4'd4: Data_out <= {8'd0, TimeStamp[63:48]}; +
-        default: Data_out <= 24'd0; +
-      endcase //A +
-      end // F=3 +
-       +
-      5'd9: begin +
-      end // F=9 +
-   +
-      5'd16: begin +
-      if (S1) begin +
-        case (A) +
-        4'd0: S800Delay <= Data_in[7:0]; +
-        4'd1: S800Width <= Data_in[7:0]; +
-        4'd2: SecondaryDelay <= Data_in[7:0]; +
-        4'd3: SecondaryWidth <= Data_in[7:0]; +
-        4'd4: S800TimingDelay <= Data_in[7:0]; +
-        4'd5: CoincTimingWidth <= Data_in[7:0]; +
-        4'd6: SecondaryTimingDelay <= Data_in[7:0]; +
-        4'd7: Bypasses <= Data_in[4:0]; +
-        4'd8: S800Factor <= Data_in[9:0]; +
-        4'd9: SecondaryFactor <= Data_in[9:0]; +
-        4'd10: TriggerBox <= Data_in[4:0]; +
-        4'd11: Go <= Data_in[0:0]; +
-        4'd12: Select <= Data_in[1:0]; +
-        4'd13: SyncEnable <= Data_in[0:0]; +
-        endcase //A +
-      end // S1=1 +
-      end // F=16 +
-         +
-      5'd17: begin +
-      if (S1) begin +
-        case (A) +
-          4'd0: Inspect1 <= Data_in[4:0]; +
-          4'd1: Inspect2 <= Data_in[4:0]; +
-          4'd2: Inspect3 <= Data_in[4:0]; +
-          4'd3: Inspect4 <= Data_in[4:0]; +
-        endcase //A +
-      end // S1=1 +
-      end // F=17 +
-         +
-      5'd18: begin +
-      if (S1) begin +
-        case (A) +
-          4'd0: ADCGate <= Data_in[7:0]; +
-          4'd1: QDCGate <= Data_in[7:0]; +
-          4'd2: TDCStart <= Data_in[7:0]; +
-          4'd3: Coincidence <= Data_in[7:0]; +
-        endcase //A +
-      end // S1=1 +
-      end // F=18 +
-        +
-    endcase // F +
-    end //N=1 +
-   +
-  end // always Clock +
-   +
-  always @(N or S1 or F or A) begin +
-    if (N) begin +
-     +
-    case (F) +
-     +
-    5'd0: begin +
-      X = 1'b1; +
-      Q = 1'b1; +
-      DriveRead = 1'b1; +
-      ClearModule = 1'b0; +
-      ClearRegister = 1'b0; +
-    end // F=0 +
-   +
-    5'd1: begin +
-      X = 1'b1; +
-      Q = 1'b1; +
-      DriveRead = 1'b1; +
-      ClearModule = 1'b0; +
-      ClearRegister = 1'b0; +
-    end // F=1 +
-   +
-    5'd2: begin +
-      X = 1'b1; +
-      Q = 1'b1; +
-      DriveRead = 1'b1; +
-      ClearModule = 1'b0; +
-      ClearRegister = 1'b0; +
-    end // F=2 +
-   +
-    5'd3: begin +
-      X = 1'b1; +
-      Q = 1'b1; +
-      DriveRead = 1'b1; +
-      ClearModule = 1'b0; +
-      ClearRegister = 1'b0; +
-    end // F=3 +
-   +
-    5'd9: begin +
-      X = 1'b1; +
-      Q = 1'b1; +
-      DriveRead = 1'b0; +
-      ClearModule = 1'b1; +
-      ClearRegister = 1'b0; +
-    end // F=9 +
-   +
-    5'd10: begin +
-      X = 1'b1; +
-      Q = 1'b1; +
-      DriveRead = 1'b0; +
-      ClearModule = 1'b0; +
-      ClearRegister = 1'b1; +
-    end // F=9 +
-   +
-    5'd16: begin +
-      X = 1'b1; +
-      Q = 1'b1; +
-      DriveRead = 1'b0; +
-      ClearModule = 1'b0; +
-      ClearRegister = 1'b0; +
-    end // F=16 +
-     +
-    5'd17: begin +
-      X = 1'b1; +
-      Q = 1'b1; +
-      DriveRead = 1'b0; +
-      ClearModule = 1'b0; +
-      ClearRegister = 1'b0; +
-    end // F=17 +
-     +
-    5'd18: begin +
-      X = 1'b1; +
-      Q = 1'b1; +
-      DriveRead = 1'b0; +
-      ClearModule = 1'b0; +
-      ClearRegister = 1'b0; +
-    end // F=18 +
-     +
-    default: begin +
-      DriveRead = 1'b0;  +
-      ClearModule = 1'b0; +
-      ClearRegister = 1'b0; +
-      X = 1'b0; +
-      Q = 1'b0; +
-    end // default F +
-   +
-    endcase // F +
-    end // if (N) +
-     +
-    else begin +
-    DriveRead = 1'b0; +
-    ClearModule = 1'b0; +
-    ClearRegister = 1'b0; +
-    X = 1'b0; +
-    Q = 1'b0; +
-    end // if (!N) +
-  end // always N or S1 or A or F +
-   +
-  endmodule +
- +
- +
- +
- +
- +
- +
- +
- +
-^ F ^ A ^ Direction ^ F ^ A ^ Direction ^ Data ^ +
-| 0 | 0  | Read | 16 | 0  | Write | S800 Gate & Delay (delay) | +
-| 0 | 1  | Read | 16 | 1  | Write | S800 Gate & Delay (width) | +
-| 0 | 2  | Read | 16 | 2  | Write | Secondary Gate & Delay (delay) | +
-| 0 | 3  | Read | 16 | 3  | Write | Secondary Gate & Delay (width) | +
-| 0 | 4  | Read | 16 | 4  | Write | S800 Delay (delay) | +
-| 0 | 5  | Read | 16 | 5  | Write | Coincidence Gate (width) | +
-| 0 | 6  | Read | 16 | 6  | Write | Secondary Delay (delay) | +
-| 0 | 7  | Read | 16 | 7  | Write | Bypasses (bit pattern) | +
-| 0 | 8  | Read | 16 | 8  | Write | S800 Downscaler (factor) | +
-| 0 | 9  | Read | 16 | 9  | Write | Secondary Downscaler (factor) | +
-| 0 | 10 | Read | 16 | 10 | Write | Trigger Box (bit pattern) | +
-| 0 | 11 | Read | 16 | 11 | Write | Go signal (bit) | +
-| 0 | 12 | Read | 16 | 12 | Write | External Time Stamp Clock (bit 0)and External Time Stamp Latch (bit 1) | +
-| 0 | 14 | Read |    |    |       | Signature 1 (0x5800) | +
-| 0 | 15 | Read |    |    |       | Signature 2 (0x2367) | +
-| 1 | 0  | Read | 17 | 0  | Write | Inspect Channel 1 (wire) | +
-| 1 | 1  | Read | 17 | 1  | Write | Inspect Channel 2 (wire) | +
-| 1 | 2  | Read | 17 | 2  | Write | Inspect Channel 3 (wire) |  +
-| 1 | 3  | Read | 17 | 3  | Write | Inspect Channel 4 (wire) | +
-| 2 | 0  | Read | 18 | 0  | Write | ADC Gate (width) | +
-| 2 | 1  | Read | 18 | 1  | Write | QDC Gate (width) | +
-| 2 | 2  | Read | 18 | 2  | Write | TDC Gate (width) | +
-| 2 | 3  | Read | 18 | 3  | Write | Coincidence Register Gate (width) | +
-| 3 | 0  | Read |    |    |       | Trigger Box Register (bit pattern) | +
-| 3 | 1  | Read |    |    |       | Time Stamp (bits 0-15) | +
-| 3 | 2  | Read |    |    |       | Time Stamp (bits 16-31) | +
-| 3 | 3  | Read |    |    |       | Time Stamp (bits 32-47) | +
-| 3 | 4  | Read |    |    |       | Time Stamp (bits 48-63) |  +
- +
- +
-==== CAMAC commands ==== +
- +
-The following table lists the CAMAC codes recognized by the trigger module and their signification.  +
- +
- +
-{|class="wikitable" +
-| F +
-| A +
-| Direction +
-| F +
-| A +
-| Direction +
-| Data +
-|- +
-| 0 +
-| 0 +
-| Read +
-| 16 +
-| 0 +
-| Write +
-| S800 Gate & Delay (delay) +
-|- +
-| 0 +
-| 1 +
-| Read +
-| 16 +
-| 1 +
-| Write +
-| S800 Gate & Delay (width) +
-|- +
-| 0 +
-| 2 +
-| Read +
-| 16 +
-| 2 +
-| Write +
-| Secondary Gate & Delay (delay) +
-|- +
-| 0 +
-| 3 +
-| Read +
-| 16 +
-| 3 +
-| Write +
-| Secondary Gate & Delay (width) +
-|- +
-| 0 +
-| 4 +
-| Read +
-| 16 +
-| 4 +
-| Write +
-| S800 Delay (delay) +
-|- +
-| 0 +
-| 5 +
-| Read +
-| 16 +
-| 5 +
-| Write +
-| Coincidence Gate (width) +
-|- +
-| 0 +
-| 6 +
-| Read +
-| 16 +
-| 6 +
-| Write +
-| Secondary Delay (delay) +
-|- +
-| 0 +
-| 7 +
-| Read +
-| 16 +
-| 7 +
-| Write +
-| Bypasses (bit pattern) +
-|- +
-| 0 +
-| 8 +
-| Read +
-| 16 +
-| 8 +
-| Write +
-| S800 Downscaler (factor) +
-|- +
-| 0 +
-| 9 +
-| Read +
-| 16 +
-| 9 +
-| Write +
-| Secondary Downscaler (factor) +
-|- +
-| 0 +
-| 10 +
-| Read +
-| 16 +
-| 10 +
-| Write +
-| Trigger Box (bit pattern) +
-|- +
-| 0 +
-| 11 +
-| Read +
-| 16 +
-| 11 +
-| Write +
-| Go signal (bit) +
-|- +
-| 0 +
-| 12 +
-| Read +
-| 16 +
-| 12 +
-| Write +
-| External Time Stamp Clock (bit 0) +
-and External Time Stamp Latch (bit 1) +
-|- +
-| 0 +
-| 14 +
-| Read +
-|  +
-|  +
-| +
-| Signature 1 (0x5800) +
-|- +
-| 0 +
-| 15 +
-| Read +
-|  +
-|  +
-| +
-| Signature 2 (0x2367) +
-|- +
-| 1 +
-| 0 +
-| Read +
-| 17 +
-| 0 +
-| Write +
-| Inspect Channel 1 (wire) +
-|- +
-| 1 +
-| 1 +
-| Read +
-| 17 +
-| 1 +
-| Write +
-| Inspect Channel 2 (wire) +
-|- +
-| 1 +
-| 2 +
-| Read +
-| 17 +
-| 2 +
-| Write +
-| Inspect Channel 3 (wire) +
-|- +
-| 1 +
-| 3 +
-| Read +
-| 17 +
-| 3 +
-| Write +
-| Inspect Channel 4 (wire) +
-|- +
-| 2 +
-| 0 +
-| Read +
-| 18 +
-| 0 +
-| Write +
-| ADC Gate (width) +
-|- +
-| 2 +
-| 1 +
-| Read +
-| 18 +
-| 1 +
-| Write +
-| QDC Gate (width) +
-|- +
-| 2 +
-| 2 +
-| Read +
-| 18 +
-| 2 +
-| Write +
-| TDC Gate (width) +
-|- +
-| 2 +
-| 3 +
-| Read +
-| 18 +
-| 3 +
-| Write +
-| Coincidence Register Gate (width) +
-|- +
-| 3 +
-| 0 +
-| Read +
-| +
-| +
-| +
-| Trigger Box Register (bit pattern) +
-|- +
-| 3 +
-| 1 +
-| Read +
-| +
-| +
-| +
-| Time Stamp (bits 0-15) +
-|- +
-| 3 +
-| 2 +
-| Read +
-| +
-| +
-| +
-| Time Stamp (bits 16-31) +
-|- +
-| 3 +
-| 3 +
-| Read +
-| +
-| +
-| +
-| Time Stamp (bits 32-47) +
-|- +
-| 3 +
-| 4 +
-| Read +
-| +
-| +
-| +
-| Time Stamp (bits 48-63) +
-|}+
  
  
 ==== Inputs and outputs ==== ==== Inputs and outputs ====
-The following table lists the inputs and outputs to/from the trigger module and their assignment.  +A table with the list of inputs/outputs channels to/from the trigger module and their assignment can be found [[Inputs and outputs | here]].
- +
-Pin  Assignment  Pin  Assignment  Pin  Assignment  Pin  Assignment   +
-A1 (in)  S800 source  B1 (out)  Raw trigger  C1 (in)  Busy 1  D1 (out)  S800 source   +
-A2 (in)  Secondary source  B2 (out)  Live trigger  C2 (in)  Busy 2  D2 (out)  Secondary source   +
-A3 (in)  External 1 source  B3 (out)  ADC gate  C3 (in)  Busy 3  D3 (out)  External 1 source   +
-A4 (in)  External 2 source  B4 (out)  QDC gate  C4 (in)  Busy 4  D4 (out)  External 2 source   +
-A5 (in)  Clear busy  B5 (out)  TDC start  C5 (in)  Busy 5  D5 (out)  S800 trigger   +
-A6 (in)  Clear module  B6 (out)  Trigger register gate  C6 (in)  Busy 6  D6 (out)  Coincidence trigger   +
-A7 (in)  Gretina sync  B7 (out)   C7 (in)  Busy 7  D7 (out)  External 1 trigger   +
-A8 (in)  Time stamp clock  B8 (out)  Live trigger  C8 (in)  Time stamp latch  D8 (out)  External 2 trigger   +
-  B9 (out)  Inspect 1  C9 (out)  Time stamp clock  D9 (out)  Secondary trigger   +
-  B10 (out)  Inspect 2  C10 (out)  Time stamp latch  D10 (out)  Raw trigger   +
-  B11 (out)  Inspect 3  C11 (out)   D11 (out)  Live trigger   +
-  B12 (out)  Inspect 4  C12 (out)   D12 (out)  Raw pulser   +
-  B13 (out)  Fast clear  C13 (out)   D13 (out)  Live pulser   +
-  B14 (out)   C14 (out)   D14 (out)  Fast clear   +
-  B15 (out)  Go  C15 (out)   D15 (out)  10 Hz   +
-  B16 (out)  Time stamp clock  C16 (out)   D16 (out)  1 Hz  +
  
 ==== FPGA firmware ==== ==== FPGA firmware ====
-The firmware of the trigger module is shown in the following files. The PDF file contains the schematic sheets, used for most of the design. The Verilog file contains the block dealing with CAMAC communications. +The firmware of the trigger module is shown in the following files. The {{:wiki:Usbtrig.pdf|PDF file}} contains the schematic sheets, used for most of the design. The [[Verilog Trigger|Verilog file]] contains the block dealing with CAMAC communications.
  
-File containing the schematics: File:Usbtrig.pdf  
  
-Below is the Verilog code used in the configuration for the INTERNAL module:  +====== Time stamping ====== 
-................ +The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger#Trigger Schematic|GUI]]). The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section "[[Trigger#Begin sequence|Begin sequence]]"). The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized. 
-....................+
  
 +The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. 
  
  
- +The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available{{:wiki:Stamp64.pdf|here. The inputs are the following: 
-====== Time stamping ====== +
-The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger#Trigger Schematic|GUI]]). The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section on [[begin sequence]]). The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized.  +
- +
-The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available [{{:wiki:Stamp64.pdf}}|here]]. The inputs are the following: +
  
 E1: time stamp clock input  E1: time stamp clock input 
trigger.txt · Last modified: 2023/10/24 16:47 by swartzj

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