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trigger [2013/12/11 15:48] pereira [FPGA firmware] |
trigger [2013/12/11 16:30] pereira [Scalers and dead time] |
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==== Time Stamping Scheme ==== | ==== Time Stamping Scheme ==== | ||
- | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping schemes are incorporated in the trigger to synchronize events. Because of this modularity, | + | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping schemes are incorporated in the trigger to synchronize events. Because of this modularity, |
+ | |||
+ | More details about the time stamping module can be found in section " | ||
===== Trigger module ===== | ===== Trigger module ===== | ||
- | The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/ | + | The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/ |
==== CAMAC commands ==== | ==== CAMAC commands ==== | ||
Line 60: | Line 62: | ||
==== FPGA firmware ==== | ==== FPGA firmware ==== | ||
- | The firmware of the trigger module is shown in the following files. The {{: | + | The firmware of the trigger module is shown in the following files. The {{: |
- | * {{: | ||
+ | ====== Time stamping ====== | ||
+ | The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger# | ||
+ | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. | ||
- | File containing the schematics: [[File: | ||
- | Below is the Verilog code used in the configuration for the INTERNAL module: | + | The time stamp module |
- | module INTERNAL (N, S1, S2, Clock, F, A, Data_in, | ||
- | DriveRead, Q, X, Data_out, | ||
- | S800Delay, S800Width, | ||
- | SecondaryDelay, | ||
- | S800TimingDelay, | ||
- | SecondaryTimingDelay, | ||
- | S800Factor, SecondaryFactor, | ||
- | ADCGate, QDCGate, TDCStart, Coincidence, | ||
- | Inspect1, Inspect2, Inspect3, Inspect4, | ||
- | Register, ClearModule, | ||
- | TimeStamp, Select, SyncEnable | ||
- | ) ; | ||
- | | ||
- | input N ; | ||
- | input S1 ; | ||
- | input S2 ; | ||
- | input Clock ; | ||
- | input [4:0] F ; | ||
- | input [3:0] A ; | ||
- | input [23:0] Data_in ; | ||
- | output Q ; | ||
- | output X ; | ||
- | output DriveRead; | ||
- | output [23:0] Data_out ; | ||
- | output [7:0] S800Delay; | ||
- | output [7:0] S800Width ; | ||
- | output [7:0] SecondaryDelay; | ||
- | output [7:0] SecondaryWidth ; | ||
- | output [7:0] S800TimingDelay; | ||
- | output [7:0] CoincTimingWidth ; | ||
- | output [7:0] SecondaryTimingDelay ; | ||
- | output [4:0] Bypasses ; | ||
- | output [9:0] S800Factor ; | ||
- | output [9:0] SecondaryFactor ; | ||
- | output [4:0] TriggerBox ; | ||
- | output [7:0] ADCGate ; | ||
- | output [7:0] QDCGate ; | ||
- | output [7:0] TDCStart ; | ||
- | output [7:0] Coincidence ; | ||
- | output [4:0] Inspect1 ; | ||
- | output [4:0] Inspect2 ; | ||
- | output [4:0] Inspect3 ; | ||
- | output [4:0] Inspect4 ; | ||
- | input [4:0] Register; | ||
- | output ClearModule; | ||
- | output ClearRegister; | ||
- | output Go; | ||
- | input [63:0] TimeStamp; | ||
- | output [1:0] Select; | ||
- | output SyncEnable; | ||
- | | ||
- | // add your declarations here | ||
- | reg X; | ||
- | reg Q; | ||
- | reg DriveRead ; | ||
- | reg ClearModule; | ||
- | reg ClearRegister; | ||
- | reg Go; | ||
- | reg [1:0] Select; | ||
- | reg SyncEnable; | ||
- | reg [23:0] Data_out ; | ||
- | reg [7:0] S800Delay; | ||
- | reg [7:0] S800Width ; | ||
- | reg [7:0] SecondaryDelay; | ||
- | reg [7:0] SecondaryWidth ; | ||
- | reg [7:0] S800TimingDelay; | ||
- | reg [7:0] CoincTimingWidth ; | ||
- | reg [7:0] SecondaryTimingDelay ; | ||
- | reg [4:0] Bypasses ; | ||
- | reg [9:0] S800Factor ; | ||
- | reg [9:0] SecondaryFactor ; | ||
- | reg [4:0] TriggerBox ; | ||
- | reg [7:0] ADCGate ; | ||
- | reg [7:0] QDCGate ; | ||
- | reg [7:0] TDCStart ; | ||
- | reg [7:0] Coincidence ; | ||
- | reg [4:0] Inspect1 ; | ||
- | reg [4:0] Inspect2 ; | ||
- | reg [4:0] Inspect3 ; | ||
- | reg [4:0] Inspect4 ; | ||
- | | ||
- | // add your code here | ||
- | always @(posedge Clock) begin | ||
- | if (N) begin | ||
- | case (F) | ||
- | 5'd0: begin | ||
- | case (A) | ||
- | 4'd0: Data_out <= {16' | ||
- | 4'd1: Data_out <= {16' | ||
- | 4'd2: Data_out <= {16' | ||
- | 4'd3: Data_out <= {16' | ||
- | 4'd4: Data_out <= {16' | ||
- | 4'd5: Data_out <= {16' | ||
- | 4'd6: Data_out <= {16' | ||
- | 4'd7: Data_out <= {19' | ||
- | 4'd8: Data_out <= {14' | ||
- | 4'd9: Data_out <= {14' | ||
- | 4'd10: Data_out <= {19' | ||
- | 4'd11: Data_out <= {23' | ||
- | 4'd12: Data_out <= {22' | ||
- | 4'd13: Data_out <= {23' | ||
- | 4'd14: Data_out <= 24' | ||
- | 4'd15: Data_out <= 24' | ||
- | default: Data_out <= 24'd0; | ||
- | endcase //A | ||
- | end // F=0 | ||
- | | ||
- | 5'd1: begin | ||
- | case (A) | ||
- | 4'd0: Data_out <= {19' | ||
- | 4'd1: Data_out <= {19' | ||
- | 4'd2: Data_out <= {19' | ||
- | 4'd3: Data_out <= {19' | ||
- | default: Data_out <= 24'd0; | ||
- | endcase //A | ||
- | end // F=1 | ||
- | | ||
- | 5'd2: begin | ||
- | case (A) | ||
- | 4'd0: Data_out <= {16' | ||
- | 4'd1: Data_out <= {16' | ||
- | 4'd2: Data_out <= {16' | ||
- | 4'd3: Data_out <= {16' | ||
- | default: Data_out <= 24'd0; | ||
- | endcase //A | ||
- | end // F=2 | ||
- | | ||
- | 5'd3: begin | ||
- | case (A) | ||
- | 4'd0: Data_out <= {19' | ||
- | 4'd1: Data_out <= {8'd0, TimeStamp[15: | ||
- | 4'd2: Data_out <= {8'd0, TimeStamp[31: | ||
- | 4'd3: Data_out <= {8'd0, TimeStamp[47: | ||
- | 4'd4: Data_out <= {8'd0, TimeStamp[63: | ||
- | default: Data_out <= 24'd0; | ||
- | endcase //A | ||
- | end // F=3 | ||
- | | ||
- | 5'd9: begin | ||
- | end // F=9 | ||
- | | ||
- | 5'd16: begin | ||
- | if (S1) begin | ||
- | case (A) | ||
- | 4'd0: S800Delay <= Data_in[7: | ||
- | 4'd1: S800Width <= Data_in[7: | ||
- | 4'd2: SecondaryDelay <= Data_in[7: | ||
- | 4'd3: SecondaryWidth <= Data_in[7: | ||
- | 4'd4: S800TimingDelay <= Data_in[7: | ||
- | 4'd5: CoincTimingWidth <= Data_in[7: | ||
- | 4'd6: SecondaryTimingDelay <= Data_in[7: | ||
- | 4'd7: Bypasses <= Data_in[4: | ||
- | 4'd8: S800Factor <= Data_in[9: | ||
- | 4'd9: SecondaryFactor <= Data_in[9: | ||
- | 4'd10: TriggerBox <= Data_in[4: | ||
- | 4'd11: Go <= Data_in[0: | ||
- | 4'd12: Select <= Data_in[1: | ||
- | 4'd13: SyncEnable <= Data_in[0: | ||
- | endcase //A | ||
- | end // S1=1 | ||
- | end // F=16 | ||
- | | ||
- | 5'd17: begin | ||
- | if (S1) begin | ||
- | case (A) | ||
- | 4'd0: Inspect1 <= Data_in[4: | ||
- | 4'd1: Inspect2 <= Data_in[4: | ||
- | 4'd2: Inspect3 <= Data_in[4: | ||
- | 4'd3: Inspect4 <= Data_in[4: | ||
- | endcase //A | ||
- | end // S1=1 | ||
- | end // F=17 | ||
- | | ||
- | 5'd18: begin | ||
- | if (S1) begin | ||
- | case (A) | ||
- | 4'd0: ADCGate <= Data_in[7: | ||
- | 4'd1: QDCGate <= Data_in[7: | ||
- | 4'd2: TDCStart <= Data_in[7: | ||
- | 4'd3: Coincidence <= Data_in[7: | ||
- | endcase //A | ||
- | end // S1=1 | ||
- | end // F=18 | ||
- | |||
- | endcase // F | ||
- | end //N=1 | ||
- | | ||
- | end // always Clock | ||
- | | ||
- | always @(N or S1 or F or A) begin | ||
- | if (N) begin | ||
- | | ||
- | case (F) | ||
- | | ||
- | 5'd0: begin | ||
- | X = 1'b1; | ||
- | Q = 1'b1; | ||
- | DriveRead = 1'b1; | ||
- | ClearModule = 1'b0; | ||
- | ClearRegister = 1'b0; | ||
- | end // F=0 | ||
- | | ||
- | 5'd1: begin | ||
- | X = 1'b1; | ||
- | Q = 1'b1; | ||
- | DriveRead = 1'b1; | ||
- | ClearModule = 1'b0; | ||
- | ClearRegister = 1'b0; | ||
- | end // F=1 | ||
- | | ||
- | 5'd2: begin | ||
- | X = 1'b1; | ||
- | Q = 1'b1; | ||
- | DriveRead = 1'b1; | ||
- | ClearModule = 1'b0; | ||
- | ClearRegister = 1'b0; | ||
- | end // F=2 | ||
- | | ||
- | 5'd3: begin | ||
- | X = 1'b1; | ||
- | Q = 1'b1; | ||
- | DriveRead = 1'b1; | ||
- | ClearModule = 1'b0; | ||
- | ClearRegister = 1'b0; | ||
- | end // F=3 | ||
- | | ||
- | 5'd9: begin | ||
- | X = 1'b1; | ||
- | Q = 1'b1; | ||
- | DriveRead = 1'b0; | ||
- | ClearModule = 1'b1; | ||
- | ClearRegister = 1'b0; | ||
- | end // F=9 | ||
- | | ||
- | 5'd10: begin | ||
- | X = 1'b1; | ||
- | Q = 1'b1; | ||
- | DriveRead = 1'b0; | ||
- | ClearModule = 1'b0; | ||
- | ClearRegister = 1'b1; | ||
- | end // F=9 | ||
- | | ||
- | 5'd16: begin | ||
- | X = 1'b1; | ||
- | Q = 1'b1; | ||
- | DriveRead = 1'b0; | ||
- | ClearModule = 1'b0; | ||
- | ClearRegister = 1'b0; | ||
- | end // F=16 | ||
- | | ||
- | 5'd17: begin | ||
- | X = 1'b1; | ||
- | Q = 1'b1; | ||
- | DriveRead = 1'b0; | ||
- | ClearModule = 1'b0; | ||
- | ClearRegister = 1'b0; | ||
- | end // F=17 | ||
- | | ||
- | 5'd18: begin | ||
- | X = 1'b1; | ||
- | Q = 1'b1; | ||
- | DriveRead = 1'b0; | ||
- | ClearModule = 1'b0; | ||
- | ClearRegister = 1'b0; | ||
- | end // F=18 | ||
- | | ||
- | default: begin | ||
- | DriveRead = 1' | ||
- | ClearModule = 1'b0; | ||
- | ClearRegister = 1'b0; | ||
- | X = 1'b0; | ||
- | Q = 1'b0; | ||
- | end // default F | ||
- | | ||
- | endcase // F | ||
- | end // if (N) | ||
- | | ||
- | else begin | ||
- | DriveRead = 1'b0; | ||
- | ClearModule = 1'b0; | ||
- | ClearRegister = 1'b0; | ||
- | X = 1'b0; | ||
- | Q = 1'b0; | ||
- | end // if (!N) | ||
- | end // always N or S1 or A or F | ||
- | | ||
- | endmodule | ||
- | |||
- | |||
- | |||
- | |||
- | |||
- | |||
- | |||
- | ==== FPGA firmware ==== | ||
- | The firmware of the trigger module is shown in the following files. The PDF file contains the schematic sheets, used for most of the design. The Verilog file contains the block dealing with CAMAC communications. | ||
- | |||
- | File containing the schematics: File: | ||
- | |||
- | Below is the Verilog code used in the configuration for the INTERNAL module: | ||
- | ................ | ||
- | .................... | ||
- | |||
- | |||
- | |||
- | |||
- | ====== Time stamping ====== | ||
- | The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger# | ||
- | |||
- | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available [{{: | ||
E1: time stamp clock input | E1: time stamp clock input | ||
Line 389: | Line 82: | ||
The clear can be done via software as well, and is usually done that way. | The clear can be done via software as well, and is usually done that way. | ||
- | Below is the Verilog | + | The [[Verilog Time stamping|Verilog file]] contains |
- | ........ | + | |
- | ........ | + | |
- | + | ||
Line 435: | Line 124: | ||
====== Begin sequence ====== | ====== Begin sequence ====== | ||
- | The internal " | + | The internal " |
- | The data acquisition begin sequence of the trigger module is the following: | + | The data acquisition begin sequence of the trigger module is the following: |
- | reset time stamp counter to 0 | + | |
- | reset trigger register to 0 | + | |
- | after all modules in all crates have been initialized, | + | |
- | after a preset delay of 200 to 300 microseconds, | + | |
- | + | ||
- | The last step of the begin sequence allows enough time for the CCUSB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the " | + | The last step of the begin sequence allows enough time for the CC-USB |
====== Scalers and dead time ====== | ====== Scalers and dead time ====== | ||
Line 450: | Line 139: | ||
In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger. | In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger. | ||
+ | The list below is a direct copy of the scaler description file for the s800. This file maps channel names to channel numbers, and in addition determines the layout. | ||
+ | |||
+ | ^ Channel name ^ Channel number ^ Channel name ^ Channel number | | ||
+ | | Live.Trigger | ||
+ | | Live.Clock | ||
+ | | S800.Source | ||
+ | | Second.Source | 1 | Second.Trigger | 8 | | ||
+ | | Ext1.Source | ||
+ | | Ext2.Source | ||
+ | | Coinc.Trigger | 5 | | | | ||
+ | | E1.Up | 16 | E1.Down | ||
+ | | E2.Up | 18 | E2.Down | ||
+ | | CRDC1.Anode | ||
+ | | TPPAC1 | ||
+ | | OBJ.Scint | ||
+ | | TAR.Scint | ||
+ | | S800.Source | ||
+ | | S800.Source | ||
+ | | S800.Source | ||
+ | | Hodo.OR | ||