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trigger [2013/12/11 15:48] pereira [FPGA firmware] |
trigger [2015/10/20 12:48] pereira [Scalers and dead time] |
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- | The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors# | + | ====== Trigger ====== |
- | The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. The main motivations for implementing the trigger logic in an FPGA driven module are the following: | + | |
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | * [[Trigger# | ||
+ | |||
+ | |||
+ | The main purpose of the trigger is to implement a coincidence between the S800 focal-plane [[Detectors# | ||
+ | |||
+ | The trigger logic is implemented in a {{: | ||
- Simplify cabling and setup of the trigger | - Simplify cabling and setup of the trigger | ||
Line 15: | Line 34: | ||
The S800 trigger from the [[Detectors# | The S800 trigger from the [[Detectors# | ||
- | + | ===== Trigger | |
- | ===== Trigger | + | |
- | The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | + | The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. The GUI is automatically displayed when clicking in the Readout icon of the [[software|u6pc5]] desktop. |
{{: | {{: | ||
Line 28: | Line 46: | ||
In addition to the singles and coincidence triggers, two separate trigger sources labeled " | In addition to the singles and coincidence triggers, two separate trigger sources labeled " | ||
- | Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" | + | Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" |
More details about the trigger box module and its FPGA schematics can be found in section " | More details about the trigger box module and its FPGA schematics can be found in section " | ||
Line 38: | Line 56: | ||
==== Inspect channels ==== | ==== Inspect channels ==== | ||
- | A set of four inspect channels are patched out to the Data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit. | + | A set of four inspect channels are patched out to the data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit. |
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==== Time Stamping Scheme ==== | ==== Time Stamping Scheme ==== | ||
- | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping schemes are incorporated in the trigger to synchronize events. Because of this modularity, | + | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping schemes are incorporated in the trigger to synchronize events. Because of this modularity, |
+ | |||
+ | More details about the time stamping module can be found in section " | ||
===== Trigger module ===== | ===== Trigger module ===== | ||
- | The S800 trigger logic is built in a LeCroy ULM2367 | + | The S800 trigger logic is built in a FPGA {{: |
==== CAMAC commands ==== | ==== CAMAC commands ==== | ||
Line 57: | Line 77: | ||
==== Inputs and outputs ==== | ==== Inputs and outputs ==== | ||
- | A table with the list of inputs/ | + | The list of inputs/ |
+ | ^ Pin ^ Assignment | ||
+ | ^ A1 (in) | S800 source | ||
+ | ^ A2 (in) | Secondary source | ||
+ | ^ A3 (in) | External 1 source ^ B3 (out) | ADC gate ^ C3 (in) | Busy 3 ^ D3 (out) | External 1 source | | ||
+ | ^ A4 (in) | External 2 source ^ B4 (out) | QDC gate ^ C4 (in) | Busy 4 ^ D4 (out) | External 2 source | | ||
+ | ^ A5 (in) | Clear busy ^ B5 (out) | TDC start ^ C5 (in) | Busy 5 ^ D5 (out) | S800 trigger | | ||
+ | ^ A6 (in) | Clear module | ||
+ | ^ A7 (in) | Gretina sync ^ B7 (out) | ^ C7 (in) | Busy 7 ^ D7 (out) | External 1 trigger | | ||
+ | ^ A8 (in) | Time stamp clock ^ B8 (out) | Live trigger | ||
+ | ^ | ||
+ | ^ | ||
+ | ^ | ||
+ | ^ | ||
+ | ^ | ||
+ | ^ | ||
+ | ^ | ||
+ | ^ | ||
==== FPGA firmware ==== | ==== FPGA firmware ==== | ||
- | The firmware of the trigger module is shown in the following files. The {{: | + | The firmware of the trigger module is shown in the following files. The {{: |
- | * {{: | ||
+ | ====== Time stamping ====== | ||
+ | The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger# | ||
+ | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. | ||
- | File containing the schematics: [[File: | ||
- | Below is the Verilog code used in the configuration for the INTERNAL module: | + | The time stamp module |
- | module INTERNAL (N, S1, S2, Clock, F, A, Data_in, | ||
- | DriveRead, Q, X, Data_out, | ||
- | S800Delay, S800Width, | ||
- | SecondaryDelay, | ||
- | S800TimingDelay, | ||
- | SecondaryTimingDelay, | ||
- | S800Factor, SecondaryFactor, | ||
- | ADCGate, QDCGate, TDCStart, Coincidence, | ||
- | Inspect1, Inspect2, Inspect3, Inspect4, | ||
- | Register, ClearModule, | ||
- | TimeStamp, Select, SyncEnable | ||
- | ) ; | ||
- | | ||
- | input N ; | ||
- | input S1 ; | ||
- | input S2 ; | ||
- | input Clock ; | ||
- | input [4:0] F ; | ||
- | input [3:0] A ; | ||
- | input [23:0] Data_in ; | ||
- | output Q ; | ||
- | output X ; | ||
- | output DriveRead; | ||
- | output [23:0] Data_out ; | ||
- | output [7:0] S800Delay; | ||
- | output [7:0] S800Width ; | ||
- | output [7:0] SecondaryDelay; | ||
- | output [7:0] SecondaryWidth ; | ||
- | output [7:0] S800TimingDelay; | ||
- | output [7:0] CoincTimingWidth ; | ||
- | output [7:0] SecondaryTimingDelay ; | ||
- | output [4:0] Bypasses ; | ||
- | output [9:0] S800Factor ; | ||
- | output [9:0] SecondaryFactor ; | ||
- | output [4:0] TriggerBox ; | ||
- | output [7:0] ADCGate ; | ||
- | output [7:0] QDCGate ; | ||
- | output [7:0] TDCStart ; | ||
- | output [7:0] Coincidence ; | ||
- | output [4:0] Inspect1 ; | ||
- | output [4:0] Inspect2 ; | ||
- | output [4:0] Inspect3 ; | ||
- | output [4:0] Inspect4 ; | ||
- | input [4:0] Register; | ||
- | output ClearModule; | ||
- | output ClearRegister; | ||
- | output Go; | ||
- | input [63:0] TimeStamp; | ||
- | output [1:0] Select; | ||
- | output SyncEnable; | ||
- | | ||
- | // add your declarations here | ||
- | reg X; | ||
- | reg Q; | ||
- | reg DriveRead ; | ||
- | reg ClearModule; | ||
- | reg ClearRegister; | ||
- | reg Go; | ||
- | reg [1:0] Select; | ||
- | reg SyncEnable; | ||
- | reg [23:0] Data_out ; | ||
- | reg [7:0] S800Delay; | ||
- | reg [7:0] S800Width ; | ||
- | reg [7:0] SecondaryDelay; | ||
- | reg [7:0] SecondaryWidth ; | ||
- | reg [7:0] S800TimingDelay; | ||
- | reg [7:0] CoincTimingWidth ; | ||
- | reg [7:0] SecondaryTimingDelay ; | ||
- | reg [4:0] Bypasses ; | ||
- | reg [9:0] S800Factor ; | ||
- | reg [9:0] SecondaryFactor ; | ||
- | reg [4:0] TriggerBox ; | ||
- | reg [7:0] ADCGate ; | ||
- | reg [7:0] QDCGate ; | ||
- | reg [7:0] TDCStart ; | ||
- | reg [7:0] Coincidence ; | ||
- | reg [4:0] Inspect1 ; | ||
- | reg [4:0] Inspect2 ; | ||
- | reg [4:0] Inspect3 ; | ||
- | reg [4:0] Inspect4 ; | ||
- | | ||
- | // add your code here | ||
- | always @(posedge Clock) begin | ||
- | if (N) begin | ||
- | case (F) | ||
- | 5'd0: begin | ||
- | case (A) | ||
- | 4'd0: Data_out <= {16' | ||
- | 4'd1: Data_out <= {16' | ||
- | 4'd2: Data_out <= {16' | ||
- | 4'd3: Data_out <= {16' | ||
- | 4'd4: Data_out <= {16' | ||
- | 4'd5: Data_out <= {16' | ||
- | 4'd6: Data_out <= {16' | ||
- | 4'd7: Data_out <= {19' | ||
- | 4'd8: Data_out <= {14' | ||
- | 4'd9: Data_out <= {14' | ||
- | 4'd10: Data_out <= {19' | ||
- | 4'd11: Data_out <= {23' | ||
- | 4'd12: Data_out <= {22' | ||
- | 4'd13: Data_out <= {23' | ||
- | 4'd14: Data_out <= 24' | ||
- | 4'd15: Data_out <= 24' | ||
- | default: Data_out <= 24'd0; | ||
- | endcase //A | ||
- | end // F=0 | ||
- | | ||
- | 5'd1: begin | ||
- | case (A) | ||
- | 4'd0: Data_out <= {19' | ||
- | 4'd1: Data_out <= {19' | ||
- | 4'd2: Data_out <= {19' | ||
- | 4'd3: Data_out <= {19' | ||
- | default: Data_out <= 24'd0; | ||
- | endcase //A | ||
- | end // F=1 | ||
- | | ||
- | 5'd2: begin | ||
- | case (A) | ||
- | 4'd0: Data_out <= {16' | ||
- | 4'd1: Data_out <= {16' | ||
- | 4'd2: Data_out <= {16' | ||
- | 4'd3: Data_out <= {16' | ||
- | default: Data_out <= 24'd0; | ||
- | endcase //A | ||
- | end // F=2 | ||
- | | ||
- | 5'd3: begin | ||
- | case (A) | ||
- | 4'd0: Data_out <= {19' | ||
- | 4'd1: Data_out <= {8'd0, TimeStamp[15: | ||
- | 4'd2: Data_out <= {8'd0, TimeStamp[31: | ||
- | 4'd3: Data_out <= {8'd0, TimeStamp[47: | ||
- | 4'd4: Data_out <= {8'd0, TimeStamp[63: | ||
- | default: Data_out <= 24'd0; | ||
- | endcase //A | ||
- | end // F=3 | ||
- | | ||
- | 5'd9: begin | ||
- | end // F=9 | ||
- | | ||
- | 5'd16: begin | ||
- | if (S1) begin | ||
- | case (A) | ||
- | 4'd0: S800Delay <= Data_in[7: | ||
- | 4'd1: S800Width <= Data_in[7: | ||
- | 4'd2: SecondaryDelay <= Data_in[7: | ||
- | 4'd3: SecondaryWidth <= Data_in[7: | ||
- | 4'd4: S800TimingDelay <= Data_in[7: | ||
- | 4'd5: CoincTimingWidth <= Data_in[7: | ||
- | 4'd6: SecondaryTimingDelay <= Data_in[7: | ||
- | 4'd7: Bypasses <= Data_in[4: | ||
- | 4'd8: S800Factor <= Data_in[9: | ||
- | 4'd9: SecondaryFactor <= Data_in[9: | ||
- | 4'd10: TriggerBox <= Data_in[4: | ||
- | 4'd11: Go <= Data_in[0: | ||
- | 4'd12: Select <= Data_in[1: | ||
- | 4'd13: SyncEnable <= Data_in[0: | ||
- | endcase //A | ||
- | end // S1=1 | ||
- | end // F=16 | ||
- | | ||
- | 5'd17: begin | ||
- | if (S1) begin | ||
- | case (A) | ||
- | 4'd0: Inspect1 <= Data_in[4: | ||
- | 4'd1: Inspect2 <= Data_in[4: | ||
- | 4'd2: Inspect3 <= Data_in[4: | ||
- | 4'd3: Inspect4 <= Data_in[4: | ||
- | endcase //A | ||
- | end // S1=1 | ||
- | end // F=17 | ||
- | | ||
- | 5'd18: begin | ||
- | if (S1) begin | ||
- | case (A) | ||
- | 4'd0: ADCGate <= Data_in[7: | ||
- | 4'd1: QDCGate <= Data_in[7: | ||
- | 4'd2: TDCStart <= Data_in[7: | ||
- | 4'd3: Coincidence <= Data_in[7: | ||
- | endcase //A | ||
- | end // S1=1 | ||
- | end // F=18 | ||
- | |||
- | endcase // F | ||
- | end //N=1 | ||
- | | ||
- | end // always Clock | ||
- | | ||
- | always @(N or S1 or F or A) begin | ||
- | if (N) begin | ||
- | | ||
- | case (F) | ||
- | | ||
- | 5'd0: begin | ||
- | X = 1'b1; | ||
- | Q = 1'b1; | ||
- | DriveRead = 1'b1; | ||
- | ClearModule = 1'b0; | ||
- | ClearRegister = 1'b0; | ||
- | end // F=0 | ||
- | | ||
- | 5'd1: begin | ||
- | X = 1'b1; | ||
- | Q = 1'b1; | ||
- | DriveRead = 1'b1; | ||
- | ClearModule = 1'b0; | ||
- | ClearRegister = 1'b0; | ||
- | end // F=1 | ||
- | | ||
- | 5'd2: begin | ||
- | X = 1'b1; | ||
- | Q = 1'b1; | ||
- | DriveRead = 1'b1; | ||
- | ClearModule = 1'b0; | ||
- | ClearRegister = 1'b0; | ||
- | end // F=2 | ||
- | | ||
- | 5'd3: begin | ||
- | X = 1'b1; | ||
- | Q = 1'b1; | ||
- | DriveRead = 1'b1; | ||
- | ClearModule = 1'b0; | ||
- | ClearRegister = 1'b0; | ||
- | end // F=3 | ||
- | | ||
- | 5'd9: begin | ||
- | X = 1'b1; | ||
- | Q = 1'b1; | ||
- | DriveRead = 1'b0; | ||
- | ClearModule = 1'b1; | ||
- | ClearRegister = 1'b0; | ||
- | end // F=9 | ||
- | | ||
- | 5'd10: begin | ||
- | X = 1'b1; | ||
- | Q = 1'b1; | ||
- | DriveRead = 1'b0; | ||
- | ClearModule = 1'b0; | ||
- | ClearRegister = 1'b1; | ||
- | end // F=9 | ||
- | | ||
- | 5'd16: begin | ||
- | X = 1'b1; | ||
- | Q = 1'b1; | ||
- | DriveRead = 1'b0; | ||
- | ClearModule = 1'b0; | ||
- | ClearRegister = 1'b0; | ||
- | end // F=16 | ||
- | | ||
- | 5'd17: begin | ||
- | X = 1'b1; | ||
- | Q = 1'b1; | ||
- | DriveRead = 1'b0; | ||
- | ClearModule = 1'b0; | ||
- | ClearRegister = 1'b0; | ||
- | end // F=17 | ||
- | | ||
- | 5'd18: begin | ||
- | X = 1'b1; | ||
- | Q = 1'b1; | ||
- | DriveRead = 1'b0; | ||
- | ClearModule = 1'b0; | ||
- | ClearRegister = 1'b0; | ||
- | end // F=18 | ||
- | | ||
- | default: begin | ||
- | DriveRead = 1' | ||
- | ClearModule = 1'b0; | ||
- | ClearRegister = 1'b0; | ||
- | X = 1'b0; | ||
- | Q = 1'b0; | ||
- | end // default F | ||
- | | ||
- | endcase // F | ||
- | end // if (N) | ||
- | | ||
- | else begin | ||
- | DriveRead = 1'b0; | ||
- | ClearModule = 1'b0; | ||
- | ClearRegister = 1'b0; | ||
- | X = 1'b0; | ||
- | Q = 1'b0; | ||
- | end // if (!N) | ||
- | end // always N or S1 or A or F | ||
- | | ||
- | endmodule | ||
- | |||
- | |||
- | |||
- | |||
- | |||
- | |||
- | |||
- | ==== FPGA firmware ==== | ||
- | The firmware of the trigger module is shown in the following files. The PDF file contains the schematic sheets, used for most of the design. The Verilog file contains the block dealing with CAMAC communications. | ||
- | |||
- | File containing the schematics: File: | ||
- | |||
- | Below is the Verilog code used in the configuration for the INTERNAL module: | ||
- | ................ | ||
- | .................... | ||
- | |||
- | |||
- | |||
- | |||
- | ====== Time stamping ====== | ||
- | The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger# | ||
- | |||
- | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available [{{: | ||
E1: time stamp clock input | E1: time stamp clock input | ||
Line 389: | Line 117: | ||
The clear can be done via software as well, and is usually done that way. | The clear can be done via software as well, and is usually done that way. | ||
- | Below is the Verilog | + | The [[Verilog Time stamping|Verilog file]] contains |
- | ........ | + | |
- | ........ | + | |
- | + | ||
Line 435: | Line 159: | ||
====== Begin sequence ====== | ====== Begin sequence ====== | ||
- | The internal " | + | The internal " |
- | The data acquisition begin sequence of the trigger module is the following: | + | The data acquisition begin sequence of the trigger module is the following: |
- | reset time stamp counter to 0 | + | |
- | reset trigger register to 0 | + | |
- | after all modules in all crates have been initialized, | + | |
- | after a preset delay of 200 to 300 microseconds, | + | |
- | + | ||
- | The last step of the begin sequence allows enough time for the CCUSB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the " | + | The last step of the begin sequence allows enough time for the CC-USB |
====== Scalers and dead time ====== | ====== Scalers and dead time ====== | ||
- | The " | + | The " |
+ | |||
+ | For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger. | ||
+ | |||
+ | The remining 16 scaler input channels (pins 17 to 32 in module) are connected to an ECL-NIM-ECL converter fed by a 16-channel {{: | ||
- | In addition, scalers are connected to the raw and live trigger signals. For the determination | + | The complete list of scaler channels can be found [[Scaler Channel Description|here]]. |