S800 Documentation

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trigger [2013/12/11 15:52]
pereira [FPGA firmware] 		trigger [2013/12/11 16:30]
pereira [Scalers and dead time]
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 ==== Time Stamping Scheme ==== ==== Time Stamping Scheme ====
-Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping schemes are incorporated in the trigger to synchronize events. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward. More details about the time stamping module can be found in section "[[Trigger#Time stamping|Time stamping]]".+Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping schemes are incorporated in the trigger to synchronize events. Because of this modularity, the same synchronization scheme can be used when coupling external data acquisition systems to the S800.
  
 +
 +More details about the time stamping module can be found in section "[[Trigger#Time stamping|Time stamping]]".
  
 ===== Trigger module ===== ===== Trigger module =====
-The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/outputs (such as the VME XLM72 module for instance). This section describes the functionality of the S800 trigger module and the commands used to control its parameters. +The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/outputs (such as the VME XLM72 module for instance). This section contains the functionality of the S800 trigger module and the commands used to control its parameters. 
  
 ==== CAMAC commands ==== ==== CAMAC commands ====
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 ====== Time stamping ====== ====== Time stamping ======
-The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger#Trigger Schematic|GUI]]). The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section on [[begin sequence]]). The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized. +The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger#Trigger Schematic|GUI]]). The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section "[[Trigger#Begin sequence|Begin sequence]]"). The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized.  
 + 
 +The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800.  
 + 
 + 
 +The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available {{:wiki:stamp64.pdf|here}}. The inputs are the following: 
  
-The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available [{{:wiki:Stamp64.pdf}}|here]]. The inputs are the following:  
  
 E1: time stamp clock input  E1: time stamp clock input 
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 The clear can be done via software as well, and is usually done that way.  The clear can be done via software as well, and is usually done that way. 
  
-Below is the Verilog code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME bus:  +The [[Verilog Time stamping|Verilog file]] contains the code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME.
-........ +
-........ +
- +
  
  
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 ====== Begin sequence ====== ====== Begin sequence ======
-The internal "Go" state of the trigger module is controlled via CAMAC commands. When "Go" is false, the trigger and time stamp clock signals are vetoed and therefore absent. This way all time stamp counters can be safely zeroed during the beginning sequence of the data acquisition systems. The last command of the CAMAC beginning sequence sets the "Go" state to true, at which point both trigger and time stamp signals are released. This mechanism ensures that all time stamp counters are synchronized. +The internal "Go" state of the trigger module is controlled via CAMAC commands. When "Go" is false, the trigger and time stamp clock signals are vetoed and therefore absent. This way all time stamp counters can be safely zeroed during the beginning sequence of the data acquisition systems. The last command of the CAMAC beginning sequence sets the "Go" state to true, at which point both trigger and time stamp signals are released. This mechanism ensures that all time stamp counters are synchronized.
  
-The data acquisition begin sequence of the trigger module is the following:  +The data acquisition begin sequence of the trigger module is the following: 
- reset time stamp counter to 0  +  - reset time stamp counter to 0 
- reset trigger register to 0  +  - reset trigger register to 0 
- after all modules in all crates have been initialized, send CAMAC command to set "Go" state to true  +  - after all modules in all crates have been initialized, send CAMAC command to set "Go" state to true 
- after a preset delay of 200 to 300 microseconds, the "Go" level is set to true  +  - after a preset delay of 200 to 300 microseconds, the "Go" level is set to true 
- +  
-The last step of the begin sequence allows enough time for the CCUSB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the "Go" state of the module back to false. +The last step of the begin sequence allows enough time for the CC-USB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the "Go" state of the module back to false.
  
 ====== Scalers and dead time ====== ====== Scalers and dead time ======
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 In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger.  In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger. 
  
 +The list below is a direct copy of the scaler description file for the s800. This file maps channel names to channel numbers, and in addition determines the layout.
 +
 +^ Channel name ^ Channel number ^ Channel name ^ Channel number |
 +| Live.Trigger  | 10  | Raw.Trigger    | 9  |
 +| Live.Clock    | 12  | Raw.Clock      | 11 |
 +| S800.Source   |  0  | S800.Trigger   | 4  |
 +| Second.Source |  1  | Second.Trigger | 8  |
 +| Ext1.Source   |  2  | Ext1.Trigger   | 6  |
 +| Ext2.Source   |  3  | Ext2.Trigger   | 7  | 
 +| Coinc.Trigger |  5  |                |    |
 +| E1.Up         | 16  | E1.Down        | 17 |
 +| E2.Up         | 18  | E2.Down        | 19 |
 +| CRDC1.Anode   | 22  | CRDC2.Anode    | 23 |
 +| TPPAC1        | 27  | TPPAC2         | 28 |
 +| OBJ.Scint     | 24  | XFP.Scint      | 25 |
 +| TAR.Scint     | 26  | XFP.Scint      | 25 |
 +| S800.Source   |  0  | OBJ.Si         | 26 |
 +| S800.Source   |  0  | OBJ.Scint      | 24 |
 +| S800.Source   |  0  | XFP.Scint      | 25 |
 +| Hodo.OR       | 30  |                |    | 
  
  
trigger.txt · Last modified: 2023/10/24 16:47 by swartzj

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