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--- trigger [2013/12/11 15:53]
pereira [Trigger module]
+++ trigger [2013/12/11 16:12]
pereira [Time stamping]
@@ Line 45: / Line 45: @@
 ==== Time Stamping Scheme ====
-Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping schemes are incorporated in the trigger to synchronize events. Because of this modularity, adding an external data acquisition system (typically from an external detector), is straightforward. More details about the time stamping module can be found in section "[[Trigger#Time stamping|Time stamping]]".
+Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping schemes are incorporated in the trigger to synchronize events. Because of this modularity, the same synchronization scheme can be used when coupling external data acquisition systems to the S800.
+More details about the time stamping module can be found in section "[[Trigger#Time stamping|Time stamping]]".
 ===== Trigger module =====
@@ Line 64: / Line 66: @@
 ====== Time stamping ======
-The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger#Trigger Schematic|GUI]]). The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section on [[begin sequence]]). The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized.
+The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger#Trigger Schematic|GUI]]). The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section "[[Trigger#Begin sequence|Begin sequence]]"). The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized.
 The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available [{{:wiki:Stamp64.pdf}}|here]]. The inputs are the following:

S800 Documentation

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