This shows you the differences between two versions of the page.
Both sides previous revision Previous revision Next revision | Previous revision Next revision Both sides next revision | ||
trigger [2013/12/11 15:53] pereira [Trigger module] |
trigger [2013/12/11 16:18] pereira [Time stamping] |
||
---|---|---|---|
Line 45: | Line 45: | ||
==== Time Stamping Scheme ==== | ==== Time Stamping Scheme ==== | ||
- | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping schemes are incorporated in the trigger to synchronize events. Because of this modularity, | + | Because the USB-based S800 data acquisition uses independent crate controllers that perform the readout in parallel, time stamping schemes are incorporated in the trigger to synchronize events. Because of this modularity, |
+ | |||
+ | More details about the time stamping module can be found in section " | ||
===== Trigger module ===== | ===== Trigger module ===== | ||
Line 64: | Line 66: | ||
====== Time stamping ====== | ====== Time stamping ====== | ||
- | The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger# | + | The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger# |
+ | |||
+ | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. | ||
+ | |||
+ | |||
+ | The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available {{: | ||
- | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available [{{: | ||
E1: time stamp clock input | E1: time stamp clock input | ||
Line 76: | Line 82: | ||
The clear can be done via software as well, and is usually done that way. | The clear can be done via software as well, and is usually done that way. | ||
- | Below is the Verilog code of the REGISTERS module of the FPGA configuration, | + | The Verilog code of the REGISTERS module of the FPGA configuration, |
- | ........ | + | |
- | ........ | + | |
- | + | ||