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trigger [2013/12/11 16:10] pereira [Time Stamping Scheme] |
trigger [2013/12/11 16:24] pereira [Begin sequence] |
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====== Time stamping ====== | ====== Time stamping ====== | ||
- | The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger# | + | The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger# |
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+ | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. | ||
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+ | The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available {{: | ||
- | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available [{{: | ||
E1: time stamp clock input | E1: time stamp clock input | ||
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The clear can be done via software as well, and is usually done that way. | The clear can be done via software as well, and is usually done that way. | ||
- | Below is the Verilog | + | The [[Verilog Time stamping|Verilog file]] contains |
- | ........ | + | |
- | ........ | + | |
- | + | ||
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====== Begin sequence ====== | ====== Begin sequence ====== | ||
- | The internal " | + | The internal " |
- | The data acquisition begin sequence of the trigger module is the following: | + | The data acquisition begin sequence of the trigger module is the following: |
- | reset time stamp counter to 0 | + | * reset time stamp counter to 0 |
- | reset trigger register to 0 | + | * reset trigger register to 0 |
- | after all modules in all crates have been initialized, | + | * after all modules in all crates have been initialized, |
- | after a preset delay of 200 to 300 microseconds, | + | * after a preset delay of 200 to 300 microseconds, |
- | The last step of the begin sequence allows enough time for the CCUSB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the " | + | The last step of the begin sequence allows enough time for the CCUSB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the " |
====== Scalers and dead time ====== | ====== Scalers and dead time ====== |