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trigger [2013/12/11 16:14] pereira [Time stamping] |
trigger [2013/12/11 16:18] pereira [Time stamping] |
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- | The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available{{: | + | The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available {{:wiki:stamp64.pdf|here}}. The inputs are the following: |
E1: time stamp clock input | E1: time stamp clock input | ||
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The clear can be done via software as well, and is usually done that way. | The clear can be done via software as well, and is usually done that way. | ||
- | Below is the Verilog code of the REGISTERS module of the FPGA configuration, | + | The Verilog code of the REGISTERS module of the FPGA configuration, |
- | ........ | + | |
- | ........ | + | |
- | + | ||