Differences

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--- trigger [2013/12/11 16:15]
pereira [Time stamping]
+++ trigger [2013/12/11 16:20]
pereira [Time stamping]
@@ Line 71: / Line 71: @@
-The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available {{:wiki:stamp64.pdf|here. The inputs are the following:
+The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available {{:wiki:stamp64.pdf|here}}. The inputs are the following:
 E1: time stamp clock input
@@ Line 81: / Line 82: @@
 The clear can be done via software as well, and is usually done that way.
-Below is the Verilog code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME bus:
+The [[Verilog Time stamping|Verilog file]] contains the code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME.
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S800 Documentation