Differences

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--- trigger [2013/12/11 16:18]
pereira [Time stamping]
+++ trigger [2013/12/11 16:20]
pereira [Time stamping]
@@ Line 82: / Line 82: @@
 The clear can be done via software as well, and is usually done that way.
-The Verilog code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME bus can be found [[here]].
+The [[Verilog Time stamping|Verilog file]] contains the code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME.

S800 Documentation