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trigger [2013/12/11 16:19]
pereira [Time stamping] |
trigger [2013/12/26 13:29]
pereira [Trigger module] |
| The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors#Plastic scintillators|E1]] and a secondary detector principally located at the target location. This coincidence is often a mandatory requirement when the trigger rate of the S800 alone (S800 singles) is too high for the data acquisition and the resulting dead time is prohibitive. | ====== Trigger ====== |
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| The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. The main motivations for implementing the trigger logic in an FPGA driven module are the following: | |
| | * [[Trigger#Trigger schematics|Trigger schematic]] |
| | * [[Trigger#Trigger box|Trigger box]] |
| | * [[Trigger#Gate generation|Gate generation]] |
| | * [[Trigger#Inspect channels|Inspect channels]] |
| | * [[Trigger#Busy Circuit|Busy Circuit]] |
| | * [[Trigger#Time Stamping Scheme|Time Stamping Scheme]] |
| | * [[Trigger#Trigger module|Trigger module]] |
| | * [[Trigger#CAMAC commands|CAMAC commands]] |
| | * [[Trigger#Inputs and outputs|Inputs and outputs]] |
| | * [[Trigger#FPGA firmware|FPGA firmware]] |
| | * [[Trigger#Time stamping|Time stamping]] |
| | * [[Trigger#Configuration for S800 in tandem with other detectors|Configuration for S800 in tandem with other detectors]] |
| | * [[Trigger#Begin sequence|Begin sequence]] |
| | * [[Trigger#Scalers and dead time|Scalers and dead time]] |
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| | The main purpose of the trigger is to implement a coincidence between the S800 focal-plane [[Detectors#Plastic scintillators|fast timing scintillator E1]] and a secondary detector generally located at the target location. This coincidence is often a mandatory requirement when the trigger rate of the S800 alone (S800 singles) is too high for the data acquisition and the resulting dead time is prohibitive. |
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| | The trigger logic is implemented in a {{:wiki:Manual_LeCroy_ULM_2367.pdf|LeCroy 2367}} Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. The main motivations for implementing the trigger logic in an FPGA driven module are the following: |
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| - Simplify cabling and setup of the trigger | - Simplify cabling and setup of the trigger |
| The S800 trigger from the [[Detectors#Plastic scintillators|E1 scintillator]] provides also the reference time for the [[Detectors#Cathode Readout Drift Chambers (CRDC)|CRDCs]] as well as time-of-flight measurements. Note that because the FPGA uses a 40 MHz internal clock, the time reference of the signals in the trigger circuit set the phase of that clock, and therefore jitter by 25 ns with respect to the source signals. This jitter is measured with a TDC and can be subtracted to the time measurements to recover the timing relative to the source signals. | The S800 trigger from the [[Detectors#Plastic scintillators|E1 scintillator]] provides also the reference time for the [[Detectors#Cathode Readout Drift Chambers (CRDC)|CRDCs]] as well as time-of-flight measurements. Note that because the FPGA uses a 40 MHz internal clock, the time reference of the signals in the trigger circuit set the phase of that clock, and therefore jitter by 25 ns with respect to the source signals. This jitter is measured with a TDC and can be subtracted to the time measurements to recover the timing relative to the source signals. |
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| | ===== Trigger schematics ===== |
| ===== Trigger schematic ===== | |
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| The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. |
| In addition to the singles and coincidence triggers, two separate trigger sources labeled "External 1" and "External 2" can be used. The various sources can be selected from the trigger box to define the raw trigger, which is then sent to a third AND gate for computer busy rejection. The busy latch (on the middle) is set by the raw trigger after a 50 ns delay, and prevents subsequent events to be accepted. It is reset by the computer once the current event has been processed. The live trigger signal feeds several gate generators which provide appropriate gates for the ADCs, QDCs, TDCs and an eventual coincidence register. Note that the trigger box contains its own coincidence register for which the input signals are delayed by 50 ns, and the gate width is set by the coincidence gate generator. The request event signal is latched before being sent to the computer. | In addition to the singles and coincidence triggers, two separate trigger sources labeled "External 1" and "External 2" can be used. The various sources can be selected from the trigger box to define the raw trigger, which is then sent to a third AND gate for computer busy rejection. The busy latch (on the middle) is set by the raw trigger after a 50 ns delay, and prevents subsequent events to be accepted. It is reset by the computer once the current event has been processed. The live trigger signal feeds several gate generators which provide appropriate gates for the ADCs, QDCs, TDCs and an eventual coincidence register. Note that the trigger box contains its own coincidence register for which the input signals are delayed by 50 ns, and the gate width is set by the coincidence gate generator. The request event signal is latched before being sent to the computer. |
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| Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" output of the trigger box may generate two pulses for a single event. A scaler connected to the "Raw trigger" output will therefore not reflect the true number of events. For this reason scalers are also connected to individual inputs of the trigger box (for more details, check the section "[[Trigger#Scalers and dead time|Scalers and dead time]]"). A trigger register word (bit pattern) is written at each occurrence of a live trigger signal. This word is the first being read out from the trigger module, prior to the time stamp ([[check trigger packet tag 0x2367 in the DAQ section for more information]]). | Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" output of the trigger box may generate two pulses for a single event. A scaler connected to the "Raw trigger" output will therefore not reflect the true number of events. For this reason scalers are also connected to individual inputs of the trigger box (for more details, check the section "[[Trigger#Scalers and dead time|Scalers and dead time]]"). A trigger register word (bit pattern) is written at each occurrence of a live trigger signal. This word is the first being read out from the trigger module, prior to the time stamp (check [[S800 USB DAQ data format#Tag 0x2367: Trigger module|trigger packet tag 0x2367]] in the DAQ section for more information). |
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| More details about the trigger box module and its FPGA schematics can be found in section "[[Trigger#Trigger module|Trigger module]]". | More details about the trigger box module and its FPGA schematics can be found in section "[[Trigger#Trigger module|Trigger module]]". |
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| ==== Inspect channels ==== | ==== Inspect channels ==== |
| A set of four inspect channels are patched out to the Data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit. | A set of four inspect channels are patched out to the data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit. |
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| ===== Trigger module ===== | ===== Trigger module ===== |
| The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/outputs (such as the VME XLM72 module for instance). This section contains the functionality of the S800 trigger module and the commands used to control its parameters. | The S800 trigger logic is built in a FPGA {{:wiki:Manual_LeCroy_ULM_2367.pdf|LeCroy 2367}} Universal Logic Module (ULM). Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/outputs (such as the VME XLM72 module for instance). This section contains the functionality of the S800 trigger module and the commands used to control its parameters. |
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| ==== CAMAC commands ==== | ==== CAMAC commands ==== |
| The clear can be done via software as well, and is usually done that way. | The clear can be done via software as well, and is usually done that way. |
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| The [[Verilog file]] contains the code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME. | The [[Verilog Time stamping|Verilog file]] contains the code of the REGISTERS module of the FPGA configuration, responsible for the communication with the VME. |
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| ====== Begin sequence ====== | ====== Begin sequence ====== |
| The internal "Go" state of the trigger module is controlled via CAMAC commands. When "Go" is false, the trigger and time stamp clock signals are vetoed and therefore absent. This way all time stamp counters can be safely zeroed during the beginning sequence of the data acquisition systems. The last command of the CAMAC beginning sequence sets the "Go" state to true, at which point both trigger and time stamp signals are released. This mechanism ensures that all time stamp counters are synchronized. | The internal "Go" state of the trigger module is controlled via CAMAC commands. When "Go" is false, the trigger and time stamp clock signals are vetoed and therefore absent. This way all time stamp counters can be safely zeroed during the beginning sequence of the data acquisition systems. The last command of the CAMAC beginning sequence sets the "Go" state to true, at which point both trigger and time stamp signals are released. This mechanism ensures that all time stamp counters are synchronized. |
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| The data acquisition begin sequence of the trigger module is the following: | The data acquisition begin sequence of the trigger module is the following: |
| reset time stamp counter to 0 | - reset time stamp counter to 0 |
| reset trigger register to 0 | - reset trigger register to 0 |
| after all modules in all crates have been initialized, send CAMAC command to set "Go" state to true | - after all modules in all crates have been initialized, send CAMAC command to set "Go" state to true |
| after a preset delay of 200 to 300 microseconds, the "Go" level is set to true | - after a preset delay of 200 to 300 microseconds, the "Go" level is set to true |
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| The last step of the begin sequence allows enough time for the CCUSB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the "Go" state of the module back to false. | The last step of the begin sequence allows enough time for the CC-USB crate controller to switch from its interactive mode to data acquisition mode. The end sequence script executed at the end of a run sets the "Go" state of the module back to false. |
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| ====== Scalers and dead time ====== | ====== Scalers and dead time ====== |
| In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger. | In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger. |
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| | The list below is a direct copy of the scaler description file for the s800. This file maps channel names to channel numbers, and in addition determines the layout. |
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| | ^ Channel name ^ Channel number ^ Channel name ^ Channel number | |
| | | Live.Trigger ^ 10 | Raw.Trigger ^ 9 | |
| | | Live.Clock ^ 12 | Raw.Clock ^ 11 | |
| | | S800.Source ^ 0 | S800.Trigger ^ 4 | |
| | | Second.Source ^ 1 | Second.Trigger ^ 8 | |
| | | Ext1.Source ^ 2 | Ext1.Trigger ^ 6 | |
| | | Ext2.Source ^ 3 | Ext2.Trigger ^ 7 | |
| | | Coinc.Trigger ^ 5 | ^ | |
| | | E1.Up ^ 16 | E1.Down ^ 17 | |
| | | E2.Up ^ 18 | E2.Down ^ 19 | |
| | | CRDC1.Anode ^ 22 | CRDC2.Anode ^ 23 | |
| | | TPPAC1 ^ 27 | TPPAC2 ^ 28 | |
| | | OBJ.Scint ^ 24 | XFP.Scint ^ 25 | |
| | | TAR.Scint ^ 26 | XFP.Scint ^ 25 | |
| | | S800.Source ^ 0 | OBJ.Si ^ 26 | |
| | | S800.Source ^ 0 | OBJ.Scint ^ 24 | |
| | | S800.Source ^ 0 | XFP.Scint ^ 25 | |
| | | Hodo.OR ^ 30 | ^ | |
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