S800 Documentation

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trigger [2013/12/12 12:29]
pereira 		trigger [2013/12/26 13:17]
pereira [Trigger]
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-   * [[Trigger#Trigger schemaatics|Trigger schematic]]+   * [[Trigger#Trigger schematics|Trigger schematic]]
      * [[Trigger#Trigger box|Trigger box]]      * [[Trigger#Trigger box|Trigger box]]
      * [[Trigger#Gate generation|Gate generation]]      * [[Trigger#Gate generation|Gate generation]]
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-The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors#Plastic scintillators|E1]] and a secondary detector principally located at the target location. This coincidence is often a mandatory requirement when the trigger rate of the S800 alone (S800 singles) is too high for the data acquisition and the resulting dead time is prohibitive. +The main purpose of the trigger is to implement a coincidence between the S800 focal-plane [[Detectors#Plastic scintillators|fast timing scintillator E1]] and a secondary detector generally located at the target location. This coincidence is often a mandatory requirement when the trigger rate of the S800 alone (S800 singles) is too high for the data acquisition and the resulting dead time is prohibitive. 
  
 The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. The main motivations for implementing the trigger logic in an FPGA driven module are the following:  The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. The main motivations for implementing the trigger logic in an FPGA driven module are the following: 
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 The S800 trigger from the [[Detectors#Plastic scintillators|E1 scintillator]] provides also the reference time for the [[Detectors#Cathode Readout Drift Chambers (CRDC)|CRDCs]] as well as time-of-flight measurements. Note that because the FPGA uses a 40 MHz internal clock, the time reference of the signals in the trigger circuit set the phase of that clock, and therefore jitter by 25 ns with respect to the source signals. This jitter is measured with a TDC and can be subtracted to the time measurements to recover the timing relative to the source signals.  The S800 trigger from the [[Detectors#Plastic scintillators|E1 scintillator]] provides also the reference time for the [[Detectors#Cathode Readout Drift Chambers (CRDC)|CRDCs]] as well as time-of-flight measurements. Note that because the FPGA uses a 40 MHz internal clock, the time reference of the signals in the trigger circuit set the phase of that clock, and therefore jitter by 25 ns with respect to the source signals. This jitter is measured with a TDC and can be subtracted to the time measurements to recover the timing relative to the source signals. 
  
-===== Trigger schematic =====+===== Trigger schematics =====
    
 The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below.  The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. 
trigger.txt ยท Last modified: 2023/10/24 16:47 by swartzj

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