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--- trigger [2013/12/21 07:38]
pereira [Trigger schematic]
+++ trigger [2014/12/01 15:26]
pereira [Trigger schematics]
@@ Line 18: / Line 18: @@
-The main purpose of the trigger is to implement a coincidence between the S800 focal-plane fast timing scintillator [[Detectors#Plastic scintillators|E1]] and a secondary detector principally located at the target location. This coincidence is often a mandatory requirement when the trigger rate of the S800 alone (S800 singles) is too high for the data acquisition and the resulting dead time is prohibitive.
+The main purpose of the trigger is to implement a coincidence between the S800 focal-plane [[Detectors#Plastic scintillators|fast timing scintillator E1]] and a secondary detector generally located at the target location. This coincidence is often a mandatory requirement when the trigger rate of the S800 alone (S800 singles) is too high for the data acquisition and the resulting dead time is prohibitive.
-The trigger logic is implemented in a LeCroy 2367 Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. The main motivations for implementing the trigger logic in an FPGA driven module are the following:
+The trigger logic is implemented in a {{:wiki:Manual_LeCroy_ULM_2367.pdf|LeCroy 2367}} Universal Logic Module (ULM) by means of its XC4000E Xilinx FPGA. The main motivations for implementing the trigger logic in an FPGA driven module are the following:
   - Simplify cabling and setup of the trigger
@@ Line 36: / Line 36: @@
 ===== Trigger schematics =====
-The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below.
+The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. The GUI is automatically displayed when clicking in the Readout icon of the [[software|u6pc5]] desktop.
 {{:wiki:TriggerGUI.png?900|Trigger schematics of the S800}}
@@ Line 46: / Line 46: @@
 In addition to the singles and coincidence triggers, two separate trigger sources labeled "External 1" and "External 2" can be used. The various sources can be selected from the trigger box to define the raw trigger, which is then sent to a third AND gate for computer busy rejection. The busy latch (on the middle) is set by the raw trigger after a 50 ns delay, and prevents subsequent events to be accepted. It is reset by the computer once the current event has been processed. The live trigger signal feeds several gate generators which provide appropriate gates for the ADCs, QDCs, TDCs and an eventual coincidence register. Note that the trigger box contains its own coincidence register for which the input signals are delayed by 50 ns, and the gate width is set by the coincidence gate generator. The request event signal is latched before being sent to the computer.
-Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" output of the trigger box may generate two pulses for a single event. A scaler connected to the "Raw trigger" output will therefore not reflect the true number of events. For this reason scalers are also connected to individual inputs of the trigger box (for more details, check the section "[[Trigger#Scalers and dead time|Scalers and dead time]]"). A trigger register word (bit pattern) is written at each occurrence of a live trigger signal. This word is the first being read out from the trigger module, prior to the time stamp ([[check trigger packet tag 0x2367 in the DAQ section for more information]]).
+Since more than one trigger source can be selected, it is possible that more than one pulse is generated at the output of the trigger box, depending on the timing and shape of the source signals. When both downscaled singles and coincidences are selected for instance, the "Raw trigger" output of the trigger box may generate two pulses for a single event. A scaler connected to the "Raw trigger" output will therefore not reflect the true number of events. For this reason scalers are also connected to individual inputs of the trigger box (for more details, check the section "[[Trigger#Scalers and dead time|Scalers and dead time]]"). A trigger register word (bit pattern) is written at each occurrence of a live trigger signal. This word is the first being read out from the trigger module, prior to the time stamp (check [[S800 USB DAQ data format#Tag 0x2367: Trigger module|trigger packet tag 0x2367]] in the DAQ section for more information).
 More details about the trigger box module and its FPGA schematics can be found in section "[[Trigger#Trigger module|Trigger module]]".
@@ Line 56: / Line 56: @@
 ==== Inspect channels ====
-A set of four inspect channels are patched out to the Data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit.
+A set of four inspect channels are patched out to the data-U6 panels. Each channel can be assigned to any connection drawn on the GUI, thereby providing a convenient way to diagnose and adjust the timings at each step of the trigger circuit.
@@ Line 69: / Line 69: @@
 ===== Trigger module =====
-The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/outputs (such as the VME XLM72 module for instance). This section contains the functionality of the S800 trigger module and the commands used to control its parameters.
+The S800 trigger logic is built in a FPGA {{:wiki:Manual_LeCroy_ULM_2367.pdf|LeCroy 2367}} Universal Logic Module (ULM). Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/outputs (such as the VME XLM72 module for instance). This section contains the functionality of the S800 trigger module and the commands used to control its parameters.
 ==== CAMAC commands ====
@@ Line 84: / Line 84: @@
 ====== Time stamping ======
-The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger#Trigger Schematic|GUI]]). The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section "[[Trigger#Begin sequence|Begin sequence]]"). The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized.
+The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger#Trigger Schematics|GUI]]). The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section "[[Trigger#Begin sequence|Begin sequence]]"). The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized.
 The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800.
@@ Line 157: / Line 157: @@
 In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger.
-The list below is a direct copy of the scaler description file for the s800. This file maps channel names to channel numbers, and in addition determines the layout.
+The remining 16 scaler input channels (pins 17 to 32 in module) are connected to a **16-channel CFD CAEN C808**, which sends the signals from the S800 detectors (**E1 up,** **E1 down**, **CRDC1**, **CRDC2**, **OBJ_SCI**, **A1900 SCI**, and **OR Hodoscope**).
+The list below is a direct copy of the scaler description file for the s800. This file maps channel names to channel numbers, and in addition determines the layout.
 ^ Channel name ^ Channel number ^ Channel name ^ Channel number |
@@ Line 177: / Line 180: @@
 | S800.Source   ^ 0 | XFP.Scint      ^ 25 |
 | Hodo.OR       ^ 30 |                ^  |
+In principle, it is possible to include other signals into the scaler channels that are not used. This requires changes in some of the tcl scripts. Make sure that you communicate with the S800 responsible, and of course, do not do anything if you don't know what you are doing. The list below describes the steps that need to be followed to include new channels in the scaler.
+  * Modify the scaler display script to include the new signals: Go to **/user/s800/Documents/Run/scalers/USBDAQ** and edit file **s800scl.des** to include the new channels (make sure that you make a copy of the old file so that it can be recovered when the new signals are not needed anymore). Save the new file.
+  * Connect the new logic signals into the free input channels of the 1**6-ch CFD CAEN C808.** Follow the output ribbon cable to know the corresponding scaler channel where the new signals from the CFD are sent.
+  * Enable the new CFD CAEN C808 channels (if they are not yet enabled): Go to **/user/s800/operations/daq/usb/Scripts** and edit file C**C0105Begin.tcl**. There ist an array variable **cfd EnableOnlyChannels** that includes the list of enabled channels. Make sure that the new channels are included. Save the new file.
+  * Start the scalers display script. You should see the new channels in the display counting. If they are zero, the CFD thresholds may be too high. If that is the case, you should lower them in file **s800cfdini.tcl** (directory **/user/s800/operations/daq/usb/Configs**).

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