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--- trigger [2013/12/26 13:27]
pereira [Inspect channels]
+++ trigger [2013/12/26 13:32]
pereira [Time stamping]
@@ Line 69: / Line 69: @@
 ===== Trigger module =====
-The S800 trigger logic is built in a LeCroy ULM2367 FPGA module. Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/outputs (such as the VME XLM72 module for instance). This section contains the functionality of the S800 trigger module and the commands used to control its parameters.
+The S800 trigger logic is built in a FPGA {{:wiki:Manual_LeCroy_ULM_2367.pdf|LeCroy 2367}} Universal Logic Module (ULM). Note that this module could be replaced in the future by another FPGA module provided it has enough NIM or ECL input/outputs (such as the VME XLM72 module for instance). This section contains the functionality of the S800 trigger module and the commands used to control its parameters.
 ==== CAMAC commands ====
@@ Line 84: / Line 84: @@
 ====== Time stamping ======
-The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger#Trigger Schematic|GUI]]). The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section "[[Trigger#Begin sequence|Begin sequence]]"). The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized.
+The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger#Trigger Schematics|GUI]]). The clock is inhibited by a "Go" signal controlled by the trigger module. While "Go" is false, all time stamp counters can be reset via CAMAC command, typically during the begin sequences of the controllers or data acquisitions (see section "[[Trigger#Begin sequence|Begin sequence]]"). The clock signal is released when the "Go" signal is set to true at the end of the begin sequence. This simple scheme insures that all time stamp counters are synchronized.
 The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800.

S800 Documentation

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