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trigger [2013/12/26 13:27] pereira [Inspect channels] |
trigger [2015/10/20 11:50] pereira [Scalers and dead time] |
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===== Trigger schematics ===== | ===== Trigger schematics ===== | ||
- | The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | + | The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. The GUI is automatically displayed when clicking in the Readout icon of the [[software|u6pc5]] desktop. |
{{: | {{: | ||
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===== Trigger module ===== | ===== Trigger module ===== | ||
- | The S800 trigger logic is built in a LeCroy ULM2367 | + | The S800 trigger logic is built in a FPGA {{: |
==== CAMAC commands ==== | ==== CAMAC commands ==== | ||
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==== Inputs and outputs ==== | ==== Inputs and outputs ==== | ||
- | A table with the list of inputs/ | + | The list of inputs/ |
+ | ^ Pin ^ Assignment | ||
+ | ^ A1 (in) | S800 source | ||
+ | ^ A2 (in) | Secondary source | ||
+ | ^ A3 (in) | External 1 source ^ B3 (out) | ADC gate ^ C3 (in) | Busy 3 ^ D3 (out) | External 1 source | | ||
+ | ^ A4 (in) | External 2 source ^ B4 (out) | QDC gate ^ C4 (in) | Busy 4 ^ D4 (out) | External 2 source | | ||
+ | ^ A5 (in) | Clear busy ^ B5 (out) | TDC start ^ C5 (in) | Busy 5 ^ D5 (out) | S800 trigger | | ||
+ | ^ A6 (in) | Clear module | ||
+ | ^ A7 (in) | Gretina sync ^ B7 (out) | ^ C7 (in) | Busy 7 ^ D7 (out) | External 1 trigger | | ||
+ | ^ A8 (in) | Time stamp clock ^ B8 (out) | Live trigger | ||
+ | ^ | ||
+ | ^ | ||
+ | ^ | ||
+ | ^ | ||
+ | ^ | ||
+ | ^ | ||
+ | ^ | ||
+ | ^ | ||
==== FPGA firmware ==== | ==== FPGA firmware ==== | ||
The firmware of the trigger module is shown in the following files. The {{: | The firmware of the trigger module is shown in the following files. The {{: | ||
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====== Time stamping ====== | ====== Time stamping ====== | ||
- | The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger# | + | The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger# |
The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. | ||
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In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger. | In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger. | ||
- | The list below is a direct copy of the scaler | + | The remining 16 scaler |
+ | |||
+ | The complete list of scaler channels can be found [[Scaler Channel Description|here]]. | ||
- | ^ Channel name ^ Channel number ^ Channel name ^ Channel number | | ||
- | | Live.Trigger | ||
- | | Live.Clock | ||
- | | S800.Source | ||
- | | Second.Source ^ 1 | Second.Trigger ^ 8 | | ||
- | | Ext1.Source | ||
- | | Ext2.Source | ||
- | | Coinc.Trigger ^ 5 | ^ | | ||
- | | E1.Up ^ 16 | E1.Down | ||
- | | E2.Up ^ 18 | E2.Down | ||
- | | CRDC1.Anode | ||
- | | TPPAC1 | ||
- | | OBJ.Scint | ||
- | | TAR.Scint | ||
- | | S800.Source | ||
- | | S800.Source | ||
- | | S800.Source | ||
- | | Hodo.OR | ||