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trigger [2014/03/11 11:20] pereira [Scalers and dead time] |
trigger [2016/03/16 15:03] pereira [Configuration for S800 in tandem with other detectors] |
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===== Trigger schematics ===== | ===== Trigger schematics ===== | ||
- | The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. | + | The trigger schematic is shown on the Graphical User Interface (GUI) displayed in the figure below. The GUI is automatically displayed when clicking in the Readout icon of the [[software|u6pc5]] desktop. |
{{: | {{: | ||
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==== Inputs and outputs ==== | ==== Inputs and outputs ==== | ||
- | A table with the list of inputs/ | + | The list of inputs/ |
+ | ^ Pin ^ Assignment | ||
+ | ^ A1 (in) | S800 source | ||
+ | ^ A2 (in) | Secondary source | ||
+ | ^ A3 (in) | External 1 source ^ B3 (out) | ADC gate ^ C3 (in) | Busy 3 ^ D3 (out) | External 1 source | | ||
+ | ^ A4 (in) | External 2 source ^ B4 (out) | QDC gate ^ C4 (in) | Busy 4 ^ D4 (out) | External 2 source | | ||
+ | ^ A5 (in) | Clear busy ^ B5 (out) | TDC start ^ C5 (in) | Busy 5 ^ D5 (out) | S800 trigger | | ||
+ | ^ A6 (in) | Clear module | ||
+ | ^ A7 (in) | Gretina sync ^ B7 (out) | ^ C7 (in) | Busy 7 ^ D7 (out) | External 1 trigger | | ||
+ | ^ A8 (in) | Time stamp clock ^ B8 (out) | Live trigger | ||
+ | ^ | ||
+ | ^ | ||
+ | ^ | ||
+ | ^ | ||
+ | ^ | ||
+ | ^ | ||
+ | ^ | ||
+ | ^ | ||
==== FPGA firmware ==== | ==== FPGA firmware ==== | ||
The firmware of the trigger module is shown in the following files. The {{: | The firmware of the trigger module is shown in the following files. The {{: | ||
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====== Time stamping ====== | ====== Time stamping ====== | ||
- | The S800 trigger provides a vetoed 10 MHz clock signal (derived from the 40 MHz FPGA clock) used for time stamping. An external clock can also be used, after selecting the appropriate check box in the [[Trigger# | + | The S800 ULM trigger |
- | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate, or in other data acquisition systems coupled to the S800. | + | The time stamping clock is available as an output that can be distributed to other time stamp modules, such as the one located in the S800 VME crate (or in other data acquisition systems coupled to the S800). The S800 VME time-stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available {{: |
- | + | ||
- | + | ||
- | The time stamp module is implemented in a XLM72 (SpartanXL) FPGA. The schematics of the firmware is available {{: | + | |
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====== Configuration for S800 in tandem with other detectors ====== | ====== Configuration for S800 in tandem with other detectors ====== | ||
- | In its standard configuration, | + | In its standard configuration, |
To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following: | To incorporate an external detector in the S800 trigger logic, the same busy and end-of-event signals are required from its data acquisition system. This is to ensure that no live trigger signal is generated when any of the partners is busy or still processing an event. The 5 signals necessary between the S800 trigger and an external data acquisition system are the following: | ||
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====== Scalers and dead time ====== | ====== Scalers and dead time ====== | ||
- | The " | + | The " |
- | + | ||
- | In addition, scalers are connected to the raw and live trigger signals. For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. This is the preferred method because the pulser is not subject to possible double triggering effects like the raw trigger. | + | |
- | + | ||
- | The remining 16 scaler input channels (pins 17 to 32 in module) are connected to a **16-channel CFD CAEN C808**, which sends the signals from the S800 detectors (**E1 up,** **E1 down**, **CRDC1**, **CRDC2**, **OBJ_SCI**, | + | |
- | + | ||
- | The list below is a direct copy of the scaler description file for the s800. This file maps channel names to channel numbers, and in addition determines the layout. | + | |
- | + | ||
- | + | ||
- | ^ Channel name ^ Channel number ^ Channel name ^ Channel number | | + | |
- | | Live.Trigger | + | |
- | | Live.Clock | + | |
- | | S800.Source | + | |
- | | Second.Source ^ 1 | Second.Trigger ^ 8 | | + | |
- | | Ext1.Source | + | |
- | | Ext2.Source | + | |
- | | Coinc.Trigger ^ 5 | ^ | | + | |
- | | E1.Up ^ 16 | E1.Down | + | |
- | | E2.Up ^ 18 | E2.Down | + | |
- | | CRDC1.Anode | + | |
- | | TPPAC1 | + | |
- | | OBJ.Scint | + | |
- | | TAR.Scint | + | |
- | | S800.Source | + | |
- | | S800.Source | + | |
- | | S800.Source | + | |
- | | Hodo.OR | + | |
- | + | ||
- | In principle, it is possible to include other signals into the scaler channels that are not used. This requires some manipulation of tcl scripts, according to the following steps: | + | |
- | + | ||
- | + | ||
- | * Modify the scaler display script to include the new signals: Go to **/ | + | |
- | + | ||
- | * Connect the new logic signals into the free input channels of the 1**6-ch CFD CAEN C808.** Follow the output ribbon cable to know the corresponding scaler channel where the new signals from the CFD are sent. | + | |
- | + | ||
- | * Enable the new CFD CAEN C808 channels (if they are not yet enabled): Go to **/ | + | |
- | * Start the scalers | + | For the determination of the dead time, both a free running and vetoed 10 kHz pulser signal are also connected to scalers. |
+ | The remining 16 scaler input channels (pins 17 to 32 in module) are connected to an ECL-NIM-ECL converter fed by a 16-channel {{: | ||
+ | The complete list of scaler channels can be found [[Scaler Channel Description|here]]. | ||