S800 Documentation

User Tools

Site Tools

Trace:
trigger

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision Both sides next revision
trigger [2014/12/01 15:26]
pereira [Trigger schematics] 		trigger [2015/10/20 11:45]
pereira [Inputs and outputs]
Line 77: Line 77:
  
 ==== Inputs and outputs ==== ==== Inputs and outputs ====
-A table with the list of inputs/outputs channels to/from the trigger module and their assignment can be found [[Inputs and outputs | here]].+The list of inputs/outputs channels to/from the ULM trigger module, and their assignment, is shown in the bale below:
  
 +^ Pin     ^ Assignment        ^ Pin       ^ Assignment            ^ Pin       ^ Assignment       ^ Pin       ^ Assignment |
 +^ A1 (in) | S800 source       ^ B1 (out)  | Raw trigger           ^ C1 (in)   | Busy 1           ^ D1 (out)  | S800 source |
 +^ A2 (in) | Secondary source  ^ B2 (out)  | Live trigger          ^ C2 (in)   | Busy 2           ^ D2 (out)  | Secondary source |
 +^ A3 (in) | External 1 source ^ B3 (out)  | ADC gate              ^ C3 (in)   | Busy 3           ^ D3 (out)  | External 1 source |
 +^ A4 (in) | External 2 source ^ B4 (out)  | QDC gate              ^ C4 (in)   | Busy 4           ^ D4 (out)  | External 2 source |
 +^ A5 (in) | Clear busy        ^ B5 (out)  | TDC start             ^ C5 (in)   | Busy 5           ^ D5 (out)  | S800 trigger |
 +^ A6 (in) | Clear module      ^ B6 (out)  | Trigger register gate ^ C6 (in)   | Busy 6           ^ D6 (out)  | Coincidence trigger |
 +^ A7 (in) | Gretina sync      ^ B7 (out)  |                       ^ C7 (in)   | Busy 7           ^ D7 (out)  | External 1 trigger |
 +^ A8 (in) | Time stamp clock  ^ B8 (out)  | Live trigger          ^ C8 (in)   | Time stamp latch ^ D8 (out)  | External 2 trigger|
 +^         |                   ^ B9 (out)  | Inspect 1             ^ C9 (out)  | Time stamp clock ^ D9 (out)  | Secondary trigger |
 +^         |                   ^ B10 (out) | Inspect 2             ^ C10 (out) | Time stamp latch ^ D10 (out) | Raw trigger |
 +^         |                   ^ B11 (out) | Inspect 3             ^ C11 (out) |                  ^ D11 (out) | Live trigger |
 +^         |                   ^ B12 (out) | Inspect 4             ^ C12 (out) |                  ^ D12 (out) | Raw pulser |
 +^         |                   ^ B13 (out) | Fast clear            ^ C13 (out) |                  ^ D13 (out) | Live pulser |
 +^         |                   ^ B14 (out) |                       ^ C14 (out) |                  ^ D14 (out) | Fast clear |
 +^         |                   ^ B15 (out) | Go                    ^ C15 (out) |                  ^ D15 (out) | 10 Hz |
 +^         |                   ^ B16 (out) | Time stamp clock      ^ C16 (out) |                  ^ D16 (out) | 1 Hz |
 ==== FPGA firmware ==== ==== FPGA firmware ====
 The firmware of the trigger module is shown in the following files. The {{:wiki:Usbtrig.pdf|PDF file}} contains the schematic sheets, used for most of the design. The [[Verilog Trigger|Verilog file]] contains the block dealing with CAMAC communications. The firmware of the trigger module is shown in the following files. The {{:wiki:Usbtrig.pdf|PDF file}} contains the schematic sheets, used for most of the design. The [[Verilog Trigger|Verilog file]] contains the block dealing with CAMAC communications.
trigger.txt ยท Last modified: 2023/10/24 16:47 by swartzj

Page Tools

Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution-Noncommercial-Share Alike 4.0 International
CC Attribution-Noncommercial-Share Alike 4.0 International Donate Powered by PHP Valid HTML5 Valid CSS Driven by DokuWiki