module Registers (
  NSELX,
  NWRX,
  ACKX,
  ADRIN,
  DATAIN,
  DATAOUT,
  DataDrive,
  Clear,
  ScalerA
  ) ;
  
  input NSELX ;
  input NWRX ;
  input ACKX ;
  input [20:2] ADRIN ;
  input [31:0] DATAIN ;
  input [63:0] ScalerA ;
  output [31:0] DATAOUT ;
  output Clear ;
  output DataDrive;
  
  // add your declarations here
  reg Clear;
  reg [31:0] DATAOUT;
  reg DataDrive;
  
  always @(NSELX or NWRX or ACKX or DATAIN or ADRIN) begin
  
    DataDrive = 0;
    DATAOUT = 32'd0;
  
  // Write from VME to FPGA
  // Addresses and Data are driven by VME
    if (!NSELX & !NWRX & !ACKX) begin
    DataDrive = 0;
    DATAOUT = 32'd0;
    case (ADRIN)
      0: Clear = DATAIN[0];
    endcase //ADRIN
    end
  
  // Read from FPGA to VME
  // Addresses driven by VME - Data driven by FPGA
    else if (!NSELX & NWRX & !ACKX) begin
    DataDrive = 1;
    case (ADRIN)
      00: DATAOUT = 32'hDABA0002;
      01: DATAOUT = ScalerA[31:0];
      02: DATAOUT = ScalerA[63:32];
      default: DATAOUT = 32'd0;
    endcase
    end
  
  // VME not accessing FPGA
    else if (NSELX & NWRX & ACKX) begin
    DataDrive = 1;
    DATAOUT = 32'd0;
    end
    
  end
  
  endmodule