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--- detectors [2016/12/28 16:36]
pereira [Cathode Readout Drift Chambers (CRDC)]
+++ detectors [2016/12/29 09:28]
pereira [Cathode Readout Drift Chambers (CRDC)]
@@ Line 19: / Line 19: @@
 Each TPPAC has an active area of 10 cm x 10 cm and is filled with isobutane at a typical __pressure of 5 torr__. The detector consists of a cathode foil with a series of aluminum strips oriented in the non-dispersive direction, followed by an anode plate and a second cathode foil with the strips oriented in the dispersive direction. A total of 128 pads are connected to the strips of each cathode foil.  The x and y positions are determined from the charge distribution on the pads. The position calibration was done using the pad pitch of 1.27 mm.
-The particles transmitted through the TPPAC ionize the gas, producing electrons and positive ions. The drift of electrons towards the central anode plane induces an image charge on the aluminum strips. The signal generated on a given pad is sent to a preamplifier, and processed by a switch capacitor array (SCA), which acts as an analogic memory. Since the signals of this detector are generated before a valid trigger occurs, they need to be temporarily recorded until the trigger is received. The SCA samples the signals from the detector with a period of 200 ns and saves the data on a continuous mode, generating an analogic buffer. When a valid trigger is received, the sampling stops and the SCA pointer moves back in the buffer by a number of samplings pre-defined according to the time passed between the tracking signal and the valid trigger. In this way, the valid trigger is correlated with the tracking signal corresponding to the same event. The reading algorithm is lead by the FPGA chips of a [[http://wwwp.cord.edu/dept/physics/mona/manuals/XLM72UM.pdf|XLM72]] VME module. The TPPACs can work at maximum rates in the range from
+The particles transmitted through the TPPAC ionize the gas, producing electrons and positive ions. The drift of electrons towards the central anode plane induces an image charge on the aluminum strips. The signal generated on a given pad is sent to a preamplifier, and processed by a switch capacitor array (SCA), which acts as an analogic memory. Since the signals of this detector are generated before a valid trigger occurs, they need to be temporarily recorded until the trigger is received. The SCA samples the signals from the detector with a period of 200 ns and saves the data on a continuous mode, generating an analogic buffer. When a valid trigger is received, the sampling stops and the SCA pointer moves back in the buffer by a number of samplings pre-defined according to the time passed between the tracking signal and the valid trigger. In this way, the valid trigger is correlated with the tracking signal corresponding to the same event. The reading algorithm is lead by the FPGA chips of a {{:wiki:Manual_JTEC_XLM72VUM.pdf|XLM72}} VME module. The TPPACs can work at maximum rates in the range from
 x 10<sup>5</sup> to 1 x 10<sup>6</sup> particles per second. The efficiency is significantly reduced for light nuclei (typically below Z=10).
@@ Line 45: / Line 45: @@
 {{:wiki:crdc-section-drift.jpg?400 |Principle of operation of a CRDC.}}
-Both  CRDCs are equipped with digital electronics, which consist of seven front-end electronic boards (FEE) designed and developed by the [[http://www.star.bnl.gov/|STAR collaboration]] ([[http://www.bnl.gov/rhic/|RHIC]]), followed by interface boards connected to a programmable FPGA VME module ({{:wiki:Manual_JTEC_XLM72VUM.pdf|XLM72}}) like the one used with the [[Detectors#Tracking Parallel Plate Avalanche Counters (TPPAC)|TPPACs]] in the intermediate image station. Each FEE includes 32 channels of preamplifier shaper, followed by a switch capacitor array (SCA) and an ADC. The processing of signals is driven by the FPGA module. Each SCA samples the signals after a valid trigger is received and sends the information into the ADC. The digitized  data are then stored into the internal memory of the FPGA and read out in block mode. The sampling frequency and number of samples read out are adjustable; typical values are 20 MHz and 8 to 12 samples. The time needed for each sampling is around 16 µs. Thus, the dead time of the electronics is directly proportional to the number of samples read out. The main advantage of the on-detector digitalization technique used with the CRDCs is the reduction of noise by avoiding the transmission of analog signals (448 from the two CRDCs) outside the vacuum chamber, and the possibility to record multi-hit events like in traditional TPC detectors. The schematic diagram of the firmware for the reading of the XLM72V FPGA can be found {{:wiki:Crdc5v.pdf|here}}
+Both  CRDCs are equipped with digital electronics, which consist of seven front-end electronic boards (FEE) designed and developed by the [[http://www.star.bnl.gov/|STAR collaboration]] ([[http://www.bnl.gov/rhic/|RHIC]]), followed by interface boards connected to a programmable FPGA VME module ({{:wiki:Manual_JTEC_XLM72VUM.pdf|XLM72}}) like the one used with the [[Detectors#Tracking Parallel Plate Avalanche Counters (TPPAC)|TPPACs]] in the intermediate image station. Each FEE includes 32 channels of preamplifier shaper, followed by a switch capacitor array (SCA) and an ADC. The processing of signals is driven by the FPGA module. Each SCA samples the signals after a valid trigger is received and sends the information into the ADC. The digitized  data are then stored into the internal memory of the FPGA and read out in block mode. The sampling frequency and number of samples read out are adjustable; typical values are 20 MHz and 8 to 12 samples. The time needed for each sampling is around 16 µs. Thus, the dead time of the electronics is directly proportional to the number of samples read out. The main advantage of the on-detector digitalization technique used with the CRDCs is the reduction of noise by avoiding the transmission of analog signals (448 from the two CRDCs) outside the vacuum chamber, and the possibility to record multi-hit events like in traditional TPC detectors. The schematic diagram of the firmware for the reading of the XLM72V FPGA can be found {{:wiki:Crdc5v.pdf|here}}.
-here

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