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s800_usb_daq_data_format [2015/10/28 18:32]
pereira [Tag 0x0DDC: Mesytec MTDC-32 module]
s800_usb_daq_data_format [2018/05/11 14:09] (current)
pereira [Tag 0x7167: Phillips 7164 ADC module for CRDC anodes (energies and TAC)]
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 ====== S800 USB DAQ data format ====== ====== S800 USB DAQ data format ======
  
-These pages contain information about the USB controller based data acquisition software of the S800. Two crates are read by the software (one CAMAC and one VME), but more could be easily added to the software.+These pages contain information about the USB controller based data acquisition software of the S800. Two crates are read by the software (one CAMAC and one VME), but more could be easily added to the software. The data format described here is irrelevant for the user. This is so because the USB data are "filtered" by the [[Event Filter|S800 Filter]] before being distributed to the user.  
  
 ===== CAMAC Crate data format ===== ===== CAMAC Crate data format =====
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 ==== Tag 0x2367: Trigger module ==== ==== Tag 0x2367: Trigger module ====
 +The [[Trigger|ULM trigger module]] provides a bit mask with information about the trigger sources, and a time-stamp value
  
 ^ 0x2367 ^ Trigger bits ^ TS 0-15 ^ TS 16-31 ^ TS 32-47 ^ TS 48-63 ^ 0xf367 | ^ 0x2367 ^ Trigger bits ^ TS 0-15 ^ TS 16-31 ^ TS 32-47 ^ TS 48-63 ^ 0xf367 |
Line 63: Line 65:
  
 {{:wiki:FERAData.png|Format of LeCroy 4300B FERA data}} {{:wiki:FERAData.png|Format of LeCroy 4300B FERA data}}
 +
 +
 +At present (Oct 2015), the FERA channel assignments are:
 +
 +^ Channel ^ Source |
 +| 0 | E1 up |
 +| 1 | E1 down |
 +| 3-15 | Free |
  
 ==== Tag 0x7164: Phillips 7164 ADC module for ion chamber energies ==== ==== Tag 0x7164: Phillips 7164 ADC module for ion chamber energies ====
Line 91: Line 101:
  
 ^ Channel ^ Assignment | ^ Channel ^ Assignment |
-| 0 | Available |+| 0 | Available (generally reserved for OBJ PIN)|
 | 1 | CRDC1 Anode | | 1 | CRDC1 Anode |
 | 2 | CRDC2 Anode | | 2 | CRDC2 Anode |
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 | 7 | XF TAC | | 7 | XF TAC |
 | 8 | Object TAC | | 8 | Object TAC |
-| 9-14 | Available |+| 9-13 | Available (generally reserved for Galotte) | 
 +14 | Available |
 | 15 | Hodoscope TAC | | 15 | Hodoscope TAC |
  
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 ^ 0x7186 ^ hit pattern ^ ADC data... ^ 0xf186 | ^ 0x7186 ^ hit pattern ^ ADC data... ^ 0xf186 |
  
-The TDC data contains all channels for which the hit pattern bit is set. The channel number is encoded in bits 12-15, while the data is in bits 0-11. The table below shows the channel assignments+The TDC data contains all channels for which the hit pattern bit is set. The channel number is encoded in bits 12-15, while the data is in bits 0-11. The channel assignments can be found [[Timing#Phillips TDC|here]]
- +
-^ Channel ^ Assignment | +
-| 0 | E1_up | +
-| 1 | E1_down | +
-| 2-7 | Available | +
-| 8 | S800 source | +
-| 9 | External 1 source | +
-| 10 | External 2 source | +
-| 11 | Secondary source | +
-| 12 | RF TOF | +
-| 13 | Object TOF | +
-| 14 | XF TOF | +
-| 15 | Available | +
  
 ==== Tag 0x4448: LeCroy4448 coincidence register module for hodoscope hit pattern ==== ==== Tag 0x4448: LeCroy4448 coincidence register module for hodoscope hit pattern ====
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 The word 0xE800 identifies the origin of the event as from the S800 VME crate The word 0xE800 identifies the origin of the event as from the S800 VME crate
  
-The following words encode the 64 bit event number+The following 4 16-bit words encode the 64 bit event number
  
 The tags and end tags identify the modules being read, and encapsulate their data. The tags, end tags and their corresponding modules are listed below: The tags and end tags identify the modules being read, and encapsulate their data. The tags, end tags and their corresponding modules are listed below:
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 ==== Tag 0x5803: XLM72 time stamp module ==== ==== Tag 0x5803: XLM72 time stamp module ====
 +The [[Trigger#Time stamping|S800 VME time-stamp module]] is implemented in a XLM72 (SpartanXL) FPGA. The coding of the time-stamp is given by:
  
 ^ 0x5803 ^ TS bits 0-15 ^ TS bits 16-31 ^ TS bits 32-47 ^ TS bits 48-63 ^ 0xF803 | ^ 0x5803 ^ TS bits 0-15 ^ TS bits 16-31 ^ TS bits 32-47 ^ TS bits 48-63 ^ 0xF803 |
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 ==== Tag 0x0DDC: Mesytec MTDC-32 module ==== ==== Tag 0x0DDC: Mesytec MTDC-32 module ====
-This module has multi-hit capabilities and a better resolution than the Phillips TDC. The format of the data is determined by the module, and schematically shown below.+The [[Timing#MTDC|Mesytec TDC module (MTDC)]] has multi-hit capabilities and a better resolution than the Phillips TDC. The format of the data is determined by the module, and schematically shown below.
  
 ^ 0x0DDC ^ Header (0-15) ^ Header (16-31) ^ Data word (0-15) ^ Data word (16-31) ^ ... ^ Ender (0-15) ^ Ender (16-31) ^ 0xFDDC | ^ 0x0DDC ^ Header (0-15) ^ Header (16-31) ^ Data word (0-15) ^ Data word (16-31) ^ ... ^ Ender (0-15) ^ Ender (16-31) ^ 0xFDDC |
  
-The number of data words depend on the number of channels receiving signals, and the number of "hits" received on each channel. The figures below illustrates how the data are coded; in the example, the MTDC window has a +The number of data words depend on the number of channels receiving signals, and the number of "hits" received on each channel. The figure below illustrates how the data are coded; in the example, the MTDC window has a 
 -1017-ns delay (with respect to the trigger trig0) and 641-ns width.  -1017-ns delay (with respect to the trigger trig0) and 641-ns width. 
  
  
-{{:wiki:MTDC_structure_diagram.jpg?500}}+{{:wiki:MTDC_structure_diagram.jpg?550}}
  
  
 Channel 0 has three consecutive hits: The second hit (time: t0,1) is processes as long as it is separated from the preceding hit (time: t0,0) by more than 160 ns (the conversion time); the third hit is not processed because it "arrived" to the MTDC after the matching window was closed. Channels 7 and 11 have a single hit each within the matching window. The resulting data structure is illustrated in the figure below: Channel 0 has three consecutive hits: The second hit (time: t0,1) is processes as long as it is separated from the preceding hit (time: t0,0) by more than 160 ns (the conversion time); the third hit is not processed because it "arrived" to the MTDC after the matching window was closed. Channels 7 and 11 have a single hit each within the matching window. The resulting data structure is illustrated in the figure below:
  
-{{:wiki:MTDC_datastructure.jpg?500}}+{{:wiki:MTDC_datastructure.jpg?1200}}
  
  
s800_usb_daq_data_format.1446071536.txt.gz · Last modified: 2015/10/28 18:32 by pereira